TSV Landing Structure with Multi-Level Mesh and Guard Ring
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Solution Overview
Problem
Modern integrated chips face challenges in forming through-substrate vias (TSVs) on thin metal landing pads without damaging them, and the use of low-k dielectrics increases reliability concerns due to fragility and moisture absorption.
Innovation Solution
A multi-level, mesh-like landing structure is implemented, where metal lines are arranged in a mesh-like fashion to distribute stress across multiple layers, and a metal guard ring structure is used to protect the dielectric surrounding the TSV and landing structure from harmful elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a through-substrate via (TSV) is formed on a thin metal landing pad, then the TSV can be connected to the metal interconnect layers, but the thin metal landing pad may be damaged or deformed during TSV formation
Solution Approach 1:
The landing pad is segmented into multiple metal layers (first metal landing pad layer and second metal landing pad layer) stacked vertically. This segmentation distributes the mechanical stress from TSV formation across multiple layers rather than concentrating it on a single thin layer, preventing damage while enabling precise TSV formation.
Solution Approach 2:
The landing pad structure uses composite materials by stacking different metal layers (e.g., copper and tungsten) with complementary properties. The softer copper layer provides stress relief during TSV formation, while the harder tungsten layer provides structural support and electrical connectivity, resolving the contradiction between forming precision and structural strength.
2Reliability
If low-k dielectric material is used to reduce signal interference, then signal integrity is improved, but the dielectric structure becomes more fragile and absorbs moisture more readily
Solution Approach 1:
A protective coating layer is applied beforehand to the low-k dielectric structure to cushion it against moisture absorption and mechanical stress. This pre-protective measure allows the use of low-k dielectric for signal integrity while compensating for its inherent fragility and moisture sensitivity.
Solution Approach 2:
The dielectric structure uses a composite approach by combining low-k dielectric material with protective coating layers and reinforced metal landing pad structures. This composite design maintains the signal integrity benefits of low-k dielectric while compensating for its structural weaknesses through additional protective elements.
3Productivity
If the metal interconnect layers are made thinner to increase device density, then chip capacity increases, but the metal landing pads become more susceptible to damage during TSV formation
Solution Approach 1:
The thin metal interconnect layers are segmented into multiple stacked landing pad layers to achieve the required device density while maintaining reliability. The vertical stacking allows thinner individual layers for high density, but the multi-layer configuration provides cumulative strength to prevent damage during TSV formation.
Data Source
AI summary
An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.