TSV Landing Pad Structure for Metal Diffusion and Alignment Control
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Solution Overview
Problem
Current semiconductor manufacturing technologies face challenges in preventing metal diffusion and side etching during TSV formation, leading to alignment abnormalities and reduced design space due to inadequate side wall protection and metal barrier layer generation.
Innovation Solution
A method involving the formation of a semiconductor structure with a TSV and a dielectric layer containing an embedded metal landing pad, where a communication hole is etched to reduce the contact area and align the metal landing pad with the TSV, using dry etching techniques to create a trapezoidal communication hole with enhanced side wall protection and passivation layers to prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a TSV insulating layer is embedded before a metal barrier layer is formed, then metal diffusion is prevented, but side etching occurs and alignment precision deteriorates
Solution Approach 1:
The TSV insulating layer is formed on the side wall of the TSV opening before the TSV bottom hole is etched through. This preliminary formation of the insulating layer prevents metal diffusion in advance, while the subsequent through-etching process maintains alignment precision by using the insulating layer as a protective barrier during the etching operation.
Solution Approach 2:
The TSV structure is divided into distinct components: the TSV opening, the TSV insulating layer formed on its side wall, and the TSV bottom hole. This segmentation allows the insulating layer to be formed and protected separately, preventing metal diffusion while maintaining precise alignment during the through-etching process.
2Ease of manufacture
If a double etching operation is performed, then the TSV insulating layer is embedded, but side etching phenomenon occurs and manufacturing precision deteriorates
Solution Approach 1:
The TSV insulating layer is formed on the side wall of the TSV opening before the through-etching operation. This preliminary formation enables the insulating layer to be embedded and protected during the subsequent etching process, achieving the embedding capability while preventing side etching through the protective barrier.
3Device complexity
If the TSV etching operation is performed with weak side wall protection, then the etching process is simplified, but side etching phenomenon occurs and reliability deteriorates
Solution Approach 1:
The TSV insulating layer is formed on the side wall of the TSV opening before the through-etching operation. This preliminary formation provides side wall protection that prevents side etching phenomenon and material transition interface damage, ensuring reliability without significantly complicating the etching process.
4Manufacturing precision
If a larger landing pad is provided, then alignment abnormality is avoided, but design space is reduced
Solution Approach 1:
The TSV insulating layer is formed on the side wall before the through-etching operation, creating a protective barrier that maintains precise alignment between the TSV opening and the metal landing pad. This allows the use of a smaller landing pad while avoiding alignment abnormalities, thereby preserving design space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces metal diffusion, improves the blocking effect of the metal barrier layer, and minimizes the size of the landing pad, thereby enhancing design efficiency and preventing chip delamination.
Implementation Method 1
forming a dielectric layer on a surface of the semiconductor substrate, the dielectric layer being provided with an embedded metal landing pad
Implementation Method 2
etching the dielectric layer to form a communication hole for communicating the TSV with the metal landing pad
Data Source
AI summary
The present application relates to the field of semiconductor technologies, and discloses a semiconductor structure and a formation method thereof. The method includes: providing a semiconductor substrate, the semiconductor substrate including a TSV; forming a dielectric layer on a surface of the semiconductor substrate, the dielectric layer being provided with an embedded metal landing pad; and etching the dielectric layer to form a communication hole for communicating the TSV with the metal landing pad.