Through Substrate Via Landing Pads for 3D Chip Stacking
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Solution Overview
Problem
The integration of 3D chip stacking faces challenges in forming through substrate vias due to high aspect ratios and the need to accurately stop the etch process to establish electrical connections, leading to yield loss from either incomplete or mechanically unstable structures.
Innovation Solution
The development of through silicon vias (TSV) with landing pads comprising multiple levels of conductive plates connected by vias, allowing for electrical connection with the TSV independent of its bottom surface location, and the use of dielectric islands to reduce polishing rate variations and mechanical instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through substrate vias are used to interconnect chips in 3D stacking, then interconnect density is improved, but manufacturing precision deteriorates due to difficulty in stopping etch process at correct depth
Solution Approach 1:
The patent applies preliminary action by forming a landing pad structure with multiple conductive plates at different depths within the substrate before etching the through-substrate via. This pre-positioned multi-level landing pad structure provides predetermined stopping points for the etch process, ensuring that even if the etch depth varies, the via will still establish electrical connection at one of the conductive plate levels, thereby resolving the manufacturing precision issue while maintaining high interconnect density
2Reliability
If through substrate vias extend completely through the substrate, then electrical connection is established, but mechanical stability deteriorates due to potential structural weakness
Solution Approach 1:
The patent employs composite materials by filling the through-substrate via with a conductive material such as copper or tungsten, and by incorporating dielectric materials in the landing pad structure. The combination of conductive fill material, dielectric surrounding layers, and multi-level conductive plates creates a composite structure that provides both reliable electrical connection and enhanced mechanical stability, preventing via collapse while maintaining conductivity
3Volume of moving object
If chips are stacked in 3D configuration, then device size is reduced, but manufacturing complexity increases due to additional interconnect formation challenges
Solution Approach 1:
The patent applies segmentation by dividing the landing pad into multiple conductive plates positioned at different depths within the substrate, rather than using a single solid block. This segmented structure simplifies the manufacturing process by providing natural etch-stopping planes and reducing the complexity of achieving precise etch depth control, while still enabling reliable electrical connection for 3D chip stacking
Data Source
AI summary
A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.