TSV Landing Structure via Segmented Interconnect Trenches
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Solution Overview
Problem
The challenge in forming a landing structure for through-silicon vias (TSVs) on the frontside of an integrated circuit die is exacerbated by dimension discrepancies between TSVs and interconnect layers, particularly for lower interconnect layers near the semiconductor substrate, where design rules are more stringent, and overlay and critical dimension variations complicate the formation of a contiguous landing structure.
Innovation Solution
The formation of a landing structure using interconnect layers involves creating a grid-patterned first trench layer and a second trench layer on top of a first via layer, with via structures disposed between the trench structures, allowing for a catch-cup configuration that receives the TSVs and providing a metallic etch stop to slow the etch process, facilitating direct electrical contact and routing of electrical signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single contiguous landing structure is formed to match TSV dimensions, then electrical connectivity is improved, but design rule compliance deteriorates due to dimension discrepancies
Solution Approach 1:
The landing structure is divided into multiple discrete interconnect features (trenches and vias) rather than a single contiguous structure. These segmented features collectively provide the landing area for the TSV while each individual feature complies with design rules. The grid pattern of trenches and vias creates a distributed landing zone that maintains electrical connectivity without requiring any single feature to exceed minimum dimensions.
Solution Approach 2:
The solution transitions from a two-dimensional planar landing pad to a three-dimensional multi-layer interconnect structure. By utilizing vertical stacking of interconnect layers with trenches and vias at different depths, the landing structure achieves the required effective area through volumetric arrangement rather than lateral expansion, thereby complying with planar design rules while providing adequate landing area.
2Manufacturing precision
If TSV dimension is reduced to match interconnect layer dimensions, then design rule compliance is improved, but TSV functionality deteriorates due to size constraints
Solution Approach 1:
The TSV landing area is segmented into multiple smaller interconnect features that collectively accommodate the full TSV dimension. Rather than constraining the TSV to a single small interconnect feature size, the TSV can maintain its larger functional dimension while landing on a distributed array of smaller trenches and vias that together provide the necessary support and electrical connection.
Solution Approach 2:
The solution changes the geometric parameters of the interconnect features (trench width, via diameter, spacing) to create a grid pattern where the collective effective area matches the TSV dimension. This allows the TSV to maintain its optimal functional size while the individual interconnect features remain within design rule limits through careful parameter optimization.
3Adaptability or versatility
If multiple interconnect layers are penetrated to reach the landing structure, then routing flexibility is improved, but process complexity deteriorates due to overlay and critical dimension variations
Solution Approach 1:
The landing structure (grid of trenches and vias) is formed in advance during the interconnect layer fabrication sequence, before the TSV backside processing occurs. This preliminary formation establishes a pre-defined landing zone that guides subsequent TSV alignment and eliminates the need for complex overlay procedures to match TSV position with landing structure position, thereby reducing process complexity while maintaining routing flexibility.
Data Source
AI summary
Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.