Through-Silicon Vias for Latch-Up Suppression in 3D ICs
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Solution Overview
Problem
In 3D integrated circuits, the increased substrate resistance due to thinning of chip substrates and the absence of backside connection in stacked configurations lead to higher susceptibility to latch-up conditions, particularly exacerbated by signal and power differences between stacked chips, which can induce latch-up through capacitive coupling.
Innovation Solution
The implementation of through-silicon vias (TSVs) that extend entirely through the substrate, with one end connected to the topside surface and the other to the backside surface, while being insulated from redistribution layer (RDL) conductors and adjacent chip features, creates a low resistance path that bypasses the substrate resistance, effectively suppressing latch-up conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip substrates are thinned to enable 3D integrated circuits, then integration density and stacking capability are improved, but substrate resistance increases leading to higher latch-up susceptibility
Solution Approach 1:
The patent introduces through-silicon vias (TSVs) that extend vertically through the thinned substrate, adding a third-dimensional conductive path. This vertical dimension bypasses the high-resistance lateral substrate paths, effectively reducing substrate resistance and latch-up susceptibility while maintaining the thinned substrate architecture necessary for 3D integration.
Solution Approach 2:
The through-silicon via acts as an intermediary conductive element that bridges the substrate front and back surfaces. By providing this intermediate conductive path, the TSV decouples the latch-up problem from the thinned substrate architecture, allowing the substrate to remain thin while still providing low-resistance current paths.
2Productivity
If substrates are thinned for 3D stacking, then manufacturing efficiency and device integration are improved, but noise coupling between stacked chips increases
Solution Approach 1:
The through-silicon via serves as an intermediary ground reference that stabilizes the substrate potential across stacked chips. By providing a direct conductive path through each substrate, the TSV reduces the impedance for noise currents and prevents noise coupling between adjacent chips in the 3D stack.
Solution Approach 2:
The through-silicon via creates equipotential regions by directly connecting the substrate front and back surfaces to common ground potentials. This reduces potential differences and voltage drops across the thinned substrate, thereby minimizing noise coupling effects between stacked devices.
3Reliability
If traditional substrate tie connections are used, then latch-up suppression is achieved in planar circuits, but these connections are insufficient for 3D stacked configurations with inter-chip voltage differences
Solution Approach 1:
The patent transitions from planar substrate ties to three-dimensional through-silicon vias. This dimensional change allows the latch-up suppression mechanism to function effectively in 3D stacked configurations, where vertical conductive paths are necessary to handle inter-chip voltage differences and maintain substrate potential stability.
Solution Approach 2:
The through-silicon via performs multiple functions: it provides latch-up suppression, establishes ground references, reduces substrate resistance, and enables compatibility with 3D stacking architectures. This multi-functionality makes the solution universally applicable to both planar and three-dimensional integrated circuit configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the likelihood of latch-up occurrences in 3D integrated circuits by providing a robust, low resistance current path that mitigates the effects of substrate thinning and inter-chip voltage differences, enhancing chip reliability and performance.
Implementation Method 1
a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface... creates a low resistance path that bypasses the substrate resistance
Implementation Method 2
The conductor in the TSV is typically copper or another metal such as TiW, and it is typically isolated from the substrate along its entire length by a dielectric or other barrier material
Data Source
AI summary
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.