TSV Interconnect Layout for Lower Capacitance in Stacked Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently connecting multiple stacked devices through through-silicon vias (TSVs) due to increased capacitance and complex interconnect structures, which can hinder performance and efficiency.
Innovation Solution
A semiconductor device design featuring a staggered layout of pad and second wirings with a unified structure of contact electrodes and wirings, utilizing a multi-layer conductive film and insulating film configuration, and a method involving dual damascene technology for precise etching and deposition to minimize capacitance and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TSV interconnect structures are used to connect stacked semiconductor devices, then electrical connectivity is achieved, but TSV capacitance increases and device complexity increases
Solution Approach 1:
The patent merges the contact electrode and wiring into a unified structure where the same conductive features serve both functions. The pad wiring directly connects to TSVs without requiring separate contact electrodes, and the third wiring continues the same conductive path through different layers, eliminating the need for distinct contact electrode structures and reducing overall interconnect complexity while maintaining electrical connectivity.
Solution Approach 2:
The conductive films in the patent perform multiple functions: the first conductive film serves as both pad wiring and contact electrode, the second conductive film functions as both TSV fill and intermediate connection, and the third conductive film acts as both wiring and connection to upper devices. This multi-functionality reduces the number of required conductive layers and simplifies the interconnect structure while ensuring reliable electrical connectivity.
2Reliability
If traditional TSV interconnect structures are used to connect stacked semiconductor devices, then electrical connectivity is achieved, but TSV capacitance increases
Solution Approach 1:
The patent extracts unnecessary conductive elements from the TSV interconnect path. By eliminating separate contact electrodes and using the pad wiring and third wiring to directly connect to TSVs, the total capacitance associated with TSV interconnect structures is reduced. The staggered layout also extracts overlapping conductive regions that would contribute to parasitic capacitance.
Solution Approach 2:
The patent employs a staggered layout where pad wirings and second wirings are offset in the horizontal dimension, and TSVs are positioned to connect between different horizontal levels. This dimensional arrangement reduces the overlap area between conductive elements, thereby reducing parasitic capacitance while maintaining vertical electrical connectivity through the stacked devices.
3Device complexity
If staggered layout with unified structure is used, then TSV capacitance is reduced and electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning actions where the first conductive film is formed with openings that define future TSV locations before the TSVs are actually formed. The second conductive film is also preliminarily patterned to create the staggered layout configuration. These preliminary actions establish precise geometric relationships that guide subsequent TSV formation and reduce alignment requirements during later manufacturing steps.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: first forming the conductive film structure with preliminary openings, then forming TSVs in separate steps, and finally completing the interconnect structure. This segmentation allows each step to be optimized independently, with the preliminary conductive film structure serving as a template that reduces precision requirements for subsequent alignment-critical steps.
Data Source
AI summary
An apparatus includes a through-silicon via (TSV) including a conductive material; a first contact plug having an upper surface and a bottom surface directly connected to an upper surface of the TSV; a first wiring directly connected to the upper surface of the first contact plug; a second wiring having an upper surface; a second contact plug having an upper surface and a bottom surface directly connected to the upper surface of the second wiring; and a third wiring directly connected to the upper surface of the second contact plug; wherein the first wiring and the third wiring are in a substantially same level.


