Through Silicon Via Layout Under Bump Metallization
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Solution Overview
Problem
The large footprint of under bump metallization (UBM) and through silicon vias (TSV) on semiconductor devices competes with trace lines for valuable surface real estate, becoming a liability as devices are scaled down.
Innovation Solution
The implementation of through silicon vias beneath an under bump metallization layer, where the UBM is electrically connected to some vias while being isolated from others, reduces the surface area required and minimizes competition with trace lines by integrating UBM and TSV in three dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If under bump metallization and through silicon vias are implemented to connect bumps to semiconductor die, then electrical connection is achieved, but surface footprint increases and competes with trace lines for valuable real estate
Solution Approach 1:
The patent moves TSV connections from the surface plane to the vertical dimension by routing them through the substrate thickness. Multiple TSVs are stacked beneath a single UBM footprint, transferring signals from the bump side to the opposite substrate side where trace lines can be routed separately. This dimensional transition eliminates surface area competition between UBM and trace lines.
Solution Approach 2:
Multiple through silicon vias are nested within the footprint area of a single under bump metallization structure. The TSVs are positioned vertically beneath the UBM, allowing multiple independent electrical connections to be packed into the space previously occupied by a single surface-level connection, thereby reducing the overall surface footprint.
2Adaptability or versatility
If multiple under bump metallizations are placed on the semiconductor die surface, then more electrical connections are provided, but they compete with trace lines for valuable surface space
Solution Approach 1:
The patent relocates multiple TSV connections to the vertical dimension beneath the substrate surface, allowing multiple UBM structures to be stacked or arranged with minimal surface overlap. Each UBM can serve multiple TSVs routed through the substrate thickness, providing enhanced adaptability for multiple electrical connections without proportionally increasing surface space requirements.
Data Source
AI summary
A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.