Resonant Clocking Using TSV-Based LC Tanks in 3D Stacked Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional resonant clocking in three-dimensional stacked devices requires valuable space on the active metal layer for inductors, reducing available routing space and memory capacity, and often necessitates additional capacitance to achieve the desired clock frequency, leading to increased costs and reduced performance.
Innovation Solution
The use of through silicon vias (TSVs) to form LC tank circuits, which provide both capacitance and inductance, allowing for resonant clocking without occupying active metal layer space and enabling sharing of resonant frequency among multiple die layers, thus optimizing space usage and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip spiral inductors are used to create resonant circuit structures, then resonant clocking can be achieved, but available routing space within the active material is reduced
Solution Approach 1:
The patent transitions from planar spiral inductors on the active metal layer to three-dimensional inductor structures formed through vertical vias and interlayer connections. This dimensional change allows the inductor to occupy vertical space rather than horizontal routing space, resolving the contradiction between achieving resonant clocking and maintaining routing availability.
2Reliability
If additional capacitance is added to bring the resonant frequency to the frequency of interest, then the desired clock frequency can be achieved, but the available space for the memory chip is further reduced
Solution Approach 1:
The patent combines the capacitor and inductor into a single integrated resonant circuit structure where the via structure serves dual purposes: providing electrical connection and forming part of the resonant tank. This merging eliminates the need for separate capacitor components and reduces the overall space required compared to discrete LC components.
Solution Approach 2:
The via structure performs multiple functions simultaneously: it provides vertical electrical interconnection between layers, serves as part of the inductor structure for resonant clocking, and replaces the need for separate capacitor components. This multi-functionality resolves the contradiction by achieving the desired clock frequency without additional space-consuming components.
3Reliability
If conventional resonant clocking is used in three-dimensional stacked devices, then clocking can be provided, but valuable space on the active metal layer is occupied, reducing available routing space and memory capacity
Solution Approach 1:
The patent implements resonant clocking structures in the vertical dimension using through-silicon vias and interlayer connections, freeing up the horizontal active metal layer space for memory cell arrays. This dimensional relocation allows both clocking functionality and maximum memory capacity to coexist without conflict.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively saves space on the active side of the die layers by utilizing TSVs to create LC tank circuits, enhancing memory capacity and reducing design and production costs while maintaining synchronous clock grids across die layers.
Implementation Method 1
a resonant circuit that is tuned to (resonates at) a clock frequency
Implementation Method 2
one or more of the through silicon vias includes a capacitive structure or an inductive structure
Implementation Method 3
one or more of the through silicon vias includes a capacitive structure or an inductive structure
Data Source
AI summary
Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.