TSV LED Packaging Structure for Compact Low-Impedance Integration
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Solution Overview
Problem
Conventional LED packaging methods, such as wire bonding, face challenges in reducing volume and impedance, making it difficult to meet the requirements of high-brightness, thin, and small applications, resulting in unsatisfactory production speed and yield.
Innovation Solution
The use of through-silicon via (TSV) technology to create a light-emitting diode packaging structure with a semiconductor substrate, insulation layer, patterned electrode layers, and conductive material, allowing for the integration of multiple LEDs in a compact and efficient manner, utilizing a metal combined substrate with a nickel-iron alloy and copper layers, and a transparent conductive layer, and employing conductive ink and silver glue for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire bonding is used to connect LED electrodes to package substrate, then electrical connection is achieved, but production speed and yield are insufficient and structure volume cannot be reduced
Solution Approach 1:
The patent merges multiple LED chips and their interconnection structures into a single integrated packaging substrate. Multiple LED chips are mounted on the substrate and electrically connected through conductive patterns and vias, eliminating the need for individual wire bonding of each LED electrode to the package substrate. This consolidation of multiple components and interconnection methods into a unified structure directly addresses the productivity issue by enabling parallel processing and assembly, while also reducing overall structural complexity.
2Volume of moving object
If wire bonding is used for LED packaging, then electrical connection is established, but the structure cannot be reduced in volume and impedance
Solution Approach 1:
The patent transitions from the traditional wire bonding approach (which extends connections in three-dimensional space with significant length) to a planar integration approach where conductive patterns and vias create direct, short-distance electrical pathways on the packaging substrate. The conductive patterns are formed in two dimensions on the substrate surface, and vias provide vertical connections in the second dimension, dramatically reducing the overall impedance and volume compared to the extended wire bonding paths.
3Productivity
If multiple light-emitting diodes are wire-bonded one by one, then each LED is connected, but production speed cannot be satisfied
Solution Approach 1:
The patent implements preliminary action by pre-forming conductive patterns and via structures on the packaging substrate before mounting the LED chips. The conductive patterns are created in advance through photolithography and etching processes, and vias are formed and filled with conductive material prior to chip assembly. This preliminary preparation of the electrical connection infrastructure allows LED chips to be mounted and connected in a streamlined, parallel process, dramatically improving production speed compared to sequential wire bonding of each LED.
Data Source
AI summary
A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.


