Through Silicon Via Load Determination Circuit
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Solution Overview
Problem
Existing semiconductor technologies are unable to accurately determine the load of through silicon vias (TSVs) in semiconductor devices, which is crucial for high-speed operation and defect detection, as they only assess the presence of defects rather than the actual load affecting signal transmission.
Innovation Solution
A semiconductor die is configured with first and second delay circuits and processing circuitry to determine the load of TSVs by generating and comparing delay signals, allowing for precise measurement of resistance, inductance, and capacitance, thereby assessing the load of TSVs connected to the circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test process is performed to determine whether a defect is present in a TSV, then defect detection capability is improved, but the ability to accurately determine the load of the TSV deteriorates
Solution Approach 1:
The invention divides the measurement function into two separate delay circuits: one dedicated to defect detection and another to load measurement. The first delay circuit includes delay stages connected in series with the TSV for defect detection, while the second delay circuit includes delay stages without TSV connection for load measurement, allowing both functions to operate independently and accurately
Solution Approach 2:
The invention introduces a transmitter as an intermediary component that generates test signals and provides them to both delay circuits. This intermediary enables the system to perform both defect detection and load measurement using a unified test signal source, coordinating the two measurement functions without interference
2Device complexity
If only defect presence is assessed in TSVs, then the test process is simple, but the ability to assess actual load affecting signal transmission deteriorates
Solution Approach 1:
The measurement system is segmented into two independent delay circuits with distinct functions. The first delay circuit maintains simplicity for defect detection by using basic delay stages, while the second delay circuit adds measurement capability for load assessment without increasing the complexity of the overall system architecture
Solution Approach 2:
The test circuit is designed with multi-functionality to perform both defect detection and load measurement. The transmitter can generate test signals for both circuits, and the processing circuitry can analyze results from both functions, allowing a single test system to serve multiple measurement purposes
Data Source
AI summary
A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.