TSV Macro Layout With Internal Boundary Cells for Narrow Channels
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Solution Overview
Problem
The challenge of efficiently designing a through silicon via (TSV) macro block in integrated circuit floorplans is exacerbated by the need for sufficient space to accommodate boundary cells, leading to redesigns and delays in product releases due to insufficient channel widths, which consume significant design time.
Innovation Solution
The use of a through silicon via macro block that includes boundary cells within its structure, allowing for reduced distance requirements between functional macros, and the implementation of a place and route tool that prevents boundary cell placement adjacent to certain sides of the TSV macro, optimizing layout and reducing the need for redesign.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary cells are placed around all sides of the TSV macro block, then manufacturability and yield are improved, but the channel width required increases significantly
Solution Approach 1:
The patent applies local quality by placing boundary cells only on specific sides of the TSV macro block (north and south sides in the vertical channel configuration) rather than uniformly on all sides. This localized approach maintains the manufacturability and yield benefits of boundary cells while reducing the total channel width requirement, as boundary cells are omitted from the east and west sides where they are not needed for process control.
2Area of stationary object
If the TSV macro block dimensions are reduced to minimize space consumption, then floorplan area utilization improves, but the keep out zone requirements cannot be satisfied
Solution Approach 1:
The patent resolves this contradiction by orienting the TSV macro block differently within the channel - specifically, by configuring the macro block so that its longer dimension is perpendicular to the channel direction rather than parallel. This dimensional reorientation allows the keep out zone to extend in the horizontal direction (perpendicular to channel flow) rather than consuming vertical channel width, thereby satisfying manufacturing precision requirements while optimizing floorplan area utilization.
3Reliability
If sufficient channel width is allocated for boundary cell placement, then design reliability improves, but design time increases due to redesign requirements
Solution Approach 1:
The patent applies preliminary action by pre-configuring the TSV macro block with boundary cells on the appropriate sides during the initial placement phase. The place and route tool is programmed to automatically recognize when a TSV macro block requires boundary cells and to allocate sufficient channel width accordingly, preventing the need for later redesign iterations and eliminating the associated time losses.
Data Source
AI summary
A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.