TSV Manufacturing via Dual CMP with Interferometry Endpoint Detection
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Solution Overview
Problem
Conventional 2D and 3D semiconductor packaging technologies face challenges with increased size and performance deterioration due to the need for longer wires and higher power consumption as more devices are integrated, which are addressed by Through-Silicon Vias (TSV) for vertical interconnections, but precise control of planarization processes is lacking.
Innovation Solution
A method for manufacturing TSVs involving a stack structure with interlayer dielectric and metal barrier layers, using chemical mechanical polishing (CMP) with varying polishing rates and endpoints determined by light interferometry or eddy currents to precisely control the removal of layers, ensuring accurate planarization and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional 2D or 3D packaging technology is used with bonding wires or contact pads to connect integrated devices, then devices can be integrated on the die, but the size of the die would be significantly increased and performance would be deteriorated
Solution Approach 1:
The patent transitions from 2D planar interconnections to 3D vertical interconnections through TSV technology. The opening penetrates through the ILD layer and substrate vertically, enabling devices to be connected in the third dimension (depth) rather than only in the plane, thus reducing the horizontal die area required for interconnections.
2Adaptability or versatility
If more devices are integrated on the die using conventional packaging technology, then device integration increases, but the contact distance increases and circuit complexity increases
Solution Approach 1:
By establishing vertical interconnection paths through TSVs, the patent reduces the horizontal distance that signals must travel. Devices stacked vertically can communicate directly through the substrate rather than requiring long horizontal wire routes, thereby simplifying the interconnection topology and reducing circuit complexity.
Solution Approach 2:
The patent extracts the interconnection function from the planar bonding wire approach and relocates it to vertical TSV structures. This separation allows the interconnection path to be independently optimized through the substrate thickness rather than being constrained by surface mounting requirements.
3Adaptability or versatility
If more devices are integrated on the die using conventional packaging technology, then device integration increases, but power consumption increases significantly
Solution Approach 1:
The vertical TSV interconnections significantly reduce the length of conductive paths compared to horizontal bonding wires. Since power consumption in interconnections is proportional to the square of the wire length (due to RC delay), the shortened vertical paths dramatically reduce power consumption for signal transmission between integrated devices.
4Speed
If TSV is used for vertical interconnections to reduce contact distance and circuit complexity, then device speed should be enhanced, but precise control of planarization processes is lacking
Solution Approach 1:
The patent implements feedback control in the CMP process by monitoring polishing rate and adjusting process parameters accordingly. The system measures the polishing rate in real-time and uses this information to control the polishing endpoint, ensuring precise removal of the metal barrier layer and insulator layer to expose the TSV opening at the correct depth.
Solution Approach 2:
The patent replaces traditional mechanical endpoint detection methods with optical interference measurement. By using light interference patterns to detect the polishing endpoint, the system achieves higher precision than mechanical sensors, enabling accurate control of the planarization process to expose TSVs at the desired depth without damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the precision and reliability of TSV formation, reducing circuit complexity, increasing device speed, and lowering power consumption by allowing precise control of the planarization process, thereby improving the overall performance and efficiency of semiconductor packaging.
Implementation Method 1
A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer
Implementation Method 2
the second planarization process has a polishing endpoint determined by a light interferometry or a motor current
Implementation Method 3
the second planarization process has a polishing endpoint determined by a light interferometry or a motor current
Data Source
AI summary
A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.