TSV Memory Controller Protocol Conversion for Low-Latency Die Stacking
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Solution Overview
Problem
High-speed communication in semiconductor devices with stacked dies via interposers leads to increased latency and power consumption.
Innovation Solution
A memory controller and semiconductor device design where core dies are stacked vertically on a logic die, communicating via through-silicon vias (TSVs), with a protocol converter performing alignment processing to convert signal protocols for multi-phase communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed communication is performed through an external interposer, then communication speed is improved, but latency increases and power consumption increases
Solution Approach 1:
The patent removes the external interposer from the communication path between the logic die and core dies. By integrating the memory controller directly onto the logic die and using TSVs for vertical communication, the system eliminates the intermediate interposer component that caused signal transmission delays and power consumption issues, while maintaining high-speed communication capabilities.
Solution Approach 2:
The patent merges the memory controller with the logic die by integrating it onto the same substrate. This consolidation allows direct communication between the memory controller and core dies through TSVs, eliminating the need for separate interposer-based communication paths and reducing both latency and power consumption.
2Speed
If high-speed communication is performed through an external interposer, then communication speed is improved, but power consumption increases
Solution Approach 1:
The patent removes the external interposer from the communication path between the logic die and core dies. By integrating the memory controller directly onto the logic die and using TSVs for vertical communication, the system eliminates the intermediate interposer component that caused signal transmission delays and power consumption issues, while maintaining high-speed communication capabilities.
Solution Approach 2:
The patent merges the memory controller with the logic die by integrating it onto the same substrate. This consolidation allows direct communication between the memory controller and core dies through TSVs, eliminating the need for separate interposer-based communication paths and reducing both latency and power consumption.
3Loss of time
If core dies are stacked vertically on logic die via TSVs, then latency is reduced and power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from a planar communication architecture to a three-dimensional vertical stacking architecture using through-silicon vias (TSVs). Core dies are stacked vertically on the logic die, enabling direct vertical communication paths that reduce signal transmission distance and latency while improving power efficiency, despite the increased fabrication complexity.
Data Source
AI summary
A semiconductor device includes at least one core die and a logic die communicating with the core die via a plurality of through-silicon vias. The logic die includes a memory controller configured to control a memory operation of the core die and a PHY region configured to receive first input signals based on a first protocol from the memory controller and transmit first output signals generated based on the first input signals to the core die via the plurality of TSVs. The PHY region includes a protocol converter configured to perform alignment processing on bits of the first input signals so as to convert the protocol of the first input signals into a second protocol and then output the first input signals based on the second protocol, wherein the second protocol supports multi-phase communication between the PHY region and the core die.