3D IC Memory Repair via TSV Spare Cell Activation
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Solution Overview
Problem
In three-dimensional integrated circuits (3-D ICs), it is challenging to repair damaged memory cells after chip stacking due to the inability to access and utilize spare memory cells, as the process of chip stacking covers the front side, making it impossible to blow fuses or activate redundant rows or columns for replacement.
Innovation Solution
A 3-D IC design that includes a controller chip with a control circuit and a memory chip with an address translation circuit featuring an external activation/enablement function, allowing the controller chip to activate unused redundant rows or columns through vertical interconnects (TSVs) after stacking to replace damaged memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chip stacking is performed using TSV technology, then the propagation delay is reduced and bandwidth is increased, but the ability to repair damaged memory cells after stacking is lost
Solution Approach 1:
The patent applies preliminary action by pre-configuring the address translation circuit and spare memory cells before stacking. The controller chip is designed with the capability to later activate spare memory cells through TSV connections, even though the actual repair activation happens after stacking. This preliminary setup enables post-stack repair functionality without compromising the speed benefits of TSV technology.
Solution Approach 2:
The address translation circuit serves as an intermediary between the controller chip and the memory chip. It mediates the communication and enables the controller to access and activate spare memory cells through the TSV connections after stacking, thus restoring repair capability without affecting the high-speed TSV interconnect.
2Adaptability or versatility
If spare memory cells are built into the memory chip before stacking, then replacement capability is provided, but the spare memory cannot be activated after stacking due to inaccessible fuse circuits
Solution Approach 1:
The patent changes the dimension of access by moving from front-side fuse blowing to back-side TSV-based activation. Instead of accessing the fuse circuit through the front side (which is blocked after stacking), the system uses TSV connections from the back side to activate spare memory cells, thus enabling operation in a different spatial dimension.
Solution Approach 2:
The address translation circuit provides multi-functionality by serving both as a normal memory address translator and as a mechanism for activating spare memory cells. This universal component enables the system to perform both standard memory operations and repair operations through the same TSV interface, simplifying the overall design.
3Ease of manufacture
If conventional laser excision programming is used, then memory cells can be programmed, but the front side of the chip becomes covered and fuse blowing is impossible after stacking
Solution Approach 1:
The patent inverts the traditional repair approach by moving the programming/activation capability from the front side to the back side. Instead of blowing fuses through the front side after stacking (which is impossible), the system activates spare memory cells through TSV connections from the back side, thus reversing the access direction to solve the accessibility problem.
Data Source
AI summary
A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked.