TSV Metal Fill Segmentation to Prevent Copper Contamination
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Solution Overview
Problem
In the manufacturing of Through-Silicon Vias (TSV), copper contamination and cracking of the silicon layer occur due to the fragility of silicon and the diffusion of copper under high temperature and electric field conditions, leading to low yield.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a groove with a first auxiliary layer and a first metal layer, where the first auxiliary layer is filled at the bottom of the groove, and subsequent thinning exposes it, preventing simultaneous grinding and reducing the risk of copper contamination and cracking, along with the use of a second metal layer that fills the opening and is annealed to manage thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the base is thinned to form TSV structures, then the interconnection distance and spacing are reduced, but copper contamination and cracking occur due to silicon fragility and copper diffusion under high temperature and electric field conditions
Solution Approach 1:
The metal layer is divided into a first metal layer and a second metal layer separated by a first auxiliary layer. The first metal layer is formed before thinning, while the second metal layer is formed after thinning and auxiliary layer removal. This segmentation allows the metal interconnection to be completed in two stages, avoiding copper contamination and cracking while maintaining short interconnection distance.
Solution Approach 2:
The first metal layer is formed in the groove before the base thinning process. This preliminary formation of the metal layer ensures that the interconnection structure is partially established before the critical thinning step, reducing the risk of copper diffusion and contamination during subsequent processing.
2Device complexity
If a single metal layer is formed in the groove, then the manufacturing process is simplified, but thermal expansion stress causes cracking and copper contamination
Solution Approach 1:
The metal interconnection is segmented into two layers with different formation timings. The first metal layer is formed before thinning, and the second metal layer is formed after thinning and auxiliary layer removal. This segmentation reduces thermal expansion stress by distributing the metal deposition across different process stages, preventing cracking and contamination.
Solution Approach 2:
The first auxiliary layer acts as an intermediary between the two metal layers. It is formed after the first metal layer, protects during the thinning process, and is removed to allow formation of the second metal layer. This intermediary structure enables the complex two-stage metal formation process while managing thermal stress.
3Reliability
If the first metal layer is formed after base thinning, then copper contamination is avoided, but the interconnection distance cannot be sufficiently reduced
Solution Approach 1:
The metal interconnection is divided into two layers formed at different stages. The first metal layer is formed before thinning to establish part of the interconnection path, and the second metal layer is formed after thinning to complete the interconnection. This segmentation allows the interconnection distance to be minimized while avoiding copper contamination through staged formation.
Solution Approach 2:
The first metal layer is preliminarily formed in the groove before the base thinning process. This preliminary action establishes the interconnection structure early, allowing subsequent thinning to reduce the overall interconnection distance while the second metal layer completes the connection without contamination risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the yield of TSV manufacturing by preventing copper contamination and cracking, ensuring precise control over the grinding process and reducing thermal stress through the use of a second metal layer with a smaller thermal expansion coefficient.
Implementation Method 1
a second metal layer that fills the opening and is annealed to manage thermal expansion
Implementation Method 2
reducing thermal stress through the use of a second metal layer with a smaller thermal expansion coefficient
Data Source
AI summary
A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.