TSV Metal Resistant to High Temperatures in Monolithic 3D IC
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Solution Overview
Problem
The challenge in integrated circuit (IC) structures is that high-temperature anneals required to activate active devices in monolithic 3D structures can damage back-end-of-line (BEOL) and far BEOL interconnect structures, leading to increased costs and process time due to the need for shielding layers.
Innovation Solution
Incorporating high-temperature resistant metals like tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, or platinum in wiring layers and through silicon vias (TSVs), allowing for higher temperature and longer duration anneals without damaging these structures, and eliminating the need for shielding layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature anneals are performed to activate active devices in monolithic 3D structures, then device activation is achieved, but BEOL and FBEOL interconnect structures are damaged
Solution Approach 1:
The patent changes the material parameter of the interconnect structures from conventional copper to high-temperature resistant metals (tungsten, cobalt, rhodium, iridium, nickel, ruthenium, tantalum, niobium, graphite, or platinum). This material substitution enables the interconnect structures to withstand the high-temperature annealing process (above 400°C) required for device activation without damage, thereby resolving the contradiction between achieving device activation and preventing interconnect damage
Solution Approach 2:
The patent employs composite material structures where high-temperature resistant metals are used in specific layers (BEOL and FBEOL interconnect layers) while allowing conventional materials to be used in other layers. This selective use of materials allows the structure to simultaneously achieve device activation through high-temperature annealing while protecting the interconnect structures from damage
2Object-affected harmful factors
If shield layers are added to protect interconnect structures during annealing, then interconnect structures are protected from damage, but costs and process time increase
Solution Approach 1:
The patent extracts and removes the shield layers from the process by directly using high-temperature resistant metals in the interconnect structures themselves. This eliminates the need for separate protective shield layers, thereby reducing both costs and process time while still providing the necessary protection against thermal damage during annealing
Solution Approach 2:
The interconnect structures perform their own protective function by being made of high-temperature resistant materials that inherently withstand the annealing process. This self-service approach eliminates the need for external shield layers, simplifying the process and reducing costs while maintaining protection against thermal damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces temperature and time constraints on anneals, prevents damage to BEOL interconnect structures, and saves costs and process time by enabling anneals to exceed 900°C without shielding, thus enhancing the reliability and efficiency of IC structure formation.
Implementation Method 1
the first wiring layer and the second wiring layer each including a first metal resistant to high temperature... allowing for higher temperature and longer duration anneals without damaging these structures
Data Source
AI summary
An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.