Through-Semiconductor Via Metal Layer Connection via Dual Patterning
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Solution Overview
Problem
Void formation and defect formation in integrated circuits due to metal ion migration and ineffective etching processes, leading to compromised electrical connections between through-semiconductor vias and subsequent metal layers, especially as feature dimensions shrink.
Innovation Solution
A method involving the formation of a semiconductor substrate with through-semiconductor vias, where a first and second pattern are etched in the interlayer dielectric layer over the vias, allowing for the embedding of interconnect vias and subsequent metal layers to be deposited in these patterns, ensuring robust electrical communication and minimizing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-semiconductor vias are formed with metal layers deposited over them, then electrical connection between vias and metal layers is achieved, but void formation occurs due to metal ion migration causing stress-induced warping
Solution Approach 1:
The patent segments the single metal layer into multiple metal layers with different materials (e.g., copper, tungsten, aluminum) deposited at different stages. This segmentation allows each layer to serve specific functions: lower layers provide electrical connection while upper layers provide structural support and prevent void formation by reducing stress concentration at the via interface.
Solution Approach 2:
The patent employs composite material structures where different metal materials are combined in vertical layers. The composite structure leverages the advantageous properties of each material: copper for high conductivity, tungsten for low stress and high mechanical strength, and aluminum for upper interconnect functionality. This composite approach prevents void formation by distributing stress across multiple material interfaces rather than concentrating it at a single via-metal interface.
2Productivity
If feature dimensions are reduced to continue scaling, then device density and integration are improved, but etching effectiveness decreases and pattern features become fragile leading to higher defect formation
Solution Approach 1:
The patent changes the physical and chemical parameters of the etching process by introducing multiple etching steps with different selectivities and conditions. Each etching step is optimized for specific features: through-via etching uses parameters optimized for deep vertical profiles, while upper interconnect etching uses parameters optimized for shallower, more lateral features. This parameter optimization maintains etching effectiveness despite overall feature size reduction.
Solution Approach 2:
The patent segments the single etching process into multiple sequential etching steps, each targeting specific features at different stages of formation. This segmentation allows each etching step to be independently optimized for its specific task, preventing the need to compromise all features to satisfy a single etching condition. The segmented approach maintains manufacturing precision while enabling continued scaling.
3Device complexity
If single patterning is used in the interlayer dielectric layer, then process complexity is minimized, but etching precision is insufficient for small feature dimensions
Solution Approach 1:
The patent segments the single patterning step into multiple sequential patterning operations, each creating specific patterns in the interlayer dielectric layer for different purposes. The first patterning creates through-via openings with precise dimensions, while subsequent patterning creates upper interconnect features. This segmentation enables each patterning step to be optimized for its specific feature type, achieving the required etching precision for small dimensions while keeping individual steps relatively simple.
Solution Approach 2:
The patent performs preliminary patterning actions to define through-via locations and dimensions before forming upper interconnect features. This preliminary action establishes a precise foundation that guides subsequent patterning steps, ensuring that all features are formed with the required precision. The preliminary patterning creates reference structures that constrain and guide later etching operations, maintaining high precision without requiring overly complex single-step patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces void formation and defect incidence, enabling reliable electrical connections and maintaining robustness as feature sizes decrease, by employing a dual patterning technique that enhances etching precision and interconnect formation.
Implementation Method 1
it is believed that void formation is attributable to migration of metal ions from the through-semiconductor vias into the interface between the through-semiconductor vias and the metal layer or dielectric layers that overlie the through-semiconductor vias
Implementation Method 2
a metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer
Data Source
AI summary
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via.