TSV Micro Bump Structure for Sub-20 Micron Chip Interconnects
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Solution Overview
Problem
Current copper pillar bump technology is unable to meet the requirements of small pitch and small size due to its process limitations, making it difficult to achieve interconnections with pitches less than 20 microns, which is necessary for advanced chip integration and miniaturization.
Innovation Solution
A method for forming micro bumps using a through silicon via (TSV) structure, where a conductive layer and connecting layer are formed within the TSV, and the silicon substrate is processed to expose the connecting layer, resulting in micro bumps with sizes less than or equal to the TSV size, enabling interconnections between chips with smaller pitches and sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If copper pillar bump technology is used, then chip bonding and interconnection are achieved, but the pitch and size cannot be reduced below 20 microns
Solution Approach 1:
The bump structure is segmented into multiple functional layers: a conductive layer (copper) for electrical connection, a connecting layer (nickel/gold) for bonding, and a micro bump structure. This segmentation allows each layer to be optimized independently, enabling the conductive layer to be smaller than traditional copper pillars while maintaining bonding capability through the connecting layer
Solution Approach 2:
The invention transitions from traditional planar bump structures to vertical TSV-based micro bump structures. By utilizing the vertical dimension through deep TSV etching and filling, the pitch between bumps can be reduced in the horizontal plane while maintaining adequate bonding area in the vertical direction, achieving sub-20-micron pitch capability
2Volume of moving object
If chip miniaturization is pursued, then packaging area and volume are reduced, but interconnection reliability becomes more difficult to ensure
Solution Approach 1:
The bump structure uses composite materials with different functions: copper for high conductivity and heat conduction, nickel for diffusion barrier and structural support, and gold for reliable bonding. This composite approach maintains interconnection reliability while reducing overall bump size and packaging volume
Solution Approach 2:
The conductive layer is nested within the TSV structure, which is embedded in the chip substrate. The connecting layer is formed on top of the conductive layer, creating a nested configuration that maximizes space utilization and reduces packaging volume while maintaining reliable electrical and mechanical connections
3Reliability
If traditional copper pillar bump is used, then bonding is achieved, but conductivity and heat conduction efficiency are insufficient
Solution Approach 1:
The conductive layer is strategically positioned and sized to provide optimal electrical and thermal pathways. The connecting layer is formulated with specific material composition (nickel and gold ratios) to enhance both mechanical bonding strength and electrical conductivity at the bonding interface, while the overall micro bump structure is minimized in size
Data Source
AI summary
A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.