TSV Microstructure Adhesion for Polymer Isolation Reliability

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Solution Overview

Problem

Existing methods for insulating through-silicon vias (TSVs) in silicon chips face challenges such as high-temperature processes damaging integrated circuits, costly deposition methods, and delamination issues with polymer layers due to insufficient bonding power, particularly on flat silicon surfaces.

Innovation Solution

A through-silicon via structure with closely-packed microstructures forming a non-random pattern on the silicon surface and sidewall, combined with a polymer local isolation layer and conductive layer, enhances adhesion and reliability by increasing contact area and using protective layers to prevent mechanical stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a polymer layer is deposited on a flat silicon surface to insulate TSV, then the insulation function is achieved, but delamination occurs due to insufficient bonding power

Engineering Contradiction:

Improveadhesion reliabilityVSAvoidbonding power

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies surface curvature by forming microstructures (protrusions and recesses) on the silicon surface instead of using a flat surface. This curvature increases the surface area and creates mechanical interlocking features that enhance polymer adhesion, directly resolving the delamination issue while maintaining manufacturing feasibility.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The patent creates a porous-like surface structure with micro-protrusions and micro-recesses on the silicon surface. This increased surface complexity provides more bonding sites and mechanical anchoring points for the polymer layer, significantly improving adhesion without requiring high-temperature processes.

Inventive Principle:

Principle #31Porous materials

2Reliability

If high-temperature process is used to deposit silicon oxide for insulation, then insulation is achieved, but integrated circuit reliability is reduced and circuit damage occurs

Engineering Contradiction:

Improveinsulation reliabilityVSAvoidcircuit damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the temperature parameter from high-temperature (around 300°C) silicon oxide deposition to low-temperature polymer deposition. This parameter change maintains the insulation function while eliminating the harmful thermal effects on the integrated circuit, directly resolving the contradiction between insulation reliability and circuit safety.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If two-dimensional blanket etching is used to roughen silicon surface, then adhesion is improved, but evenness of roughening cannot be controlled

Engineering Contradiction:

Improveadhesion reliabilityVSAvoidroughening evenness

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the surface roughening process into localized microstructures (individual protrusions and recesses) rather than applying uniform two-dimensional blanket etching. This segmentation allows for better control of roughening evenness while maintaining adhesion improvement, as each microstructure can be more precisely controlled than a blanket etch.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively promotes adhesion of the isolation layer to the silicon surface, improving the reliability and reducing mechanical stress, thereby enhancing the electrical path and package reliability without the need for high-temperature processes.

Implementation Method 1

a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip

Methodology Applied

Scientific EffectSurface area increase through microstructures:

Implementation Method 2

by chemical vapor deposition (CVD) of the polymer

Methodology Applied

Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS8791578B2Through-silicon via structure with patterned surface, patterned sidewall and local isolation

Publication Date: 2014.07.29 HONG KONG APPLIED SCI & TECH RES INST

AI summary

This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 μm.