Multi-chip Memory Stacking with TSV Signal Paths
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Solution Overview
Problem
Existing multi-chip memory devices face inefficiencies in controlling read/write operations across stacked memory chips, particularly due to limitations in signal path implementation, which affects data storage capacity and bandwidth per unit surface area.
Innovation Solution
The use of through silicon vias (TSVs) to establish signal paths that communicate input/output signals across stacked memory chips, allowing for common addressing and vertical alignment of memory banks for efficient read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bonding wire connection techniques are used to stack memory chips, then the device structure is simpler to manufacture, but the data storage capacity and bandwidth per unit surface area are limited
Solution Approach 1:
The patent transitions from planar chip arrangement to vertical stacking architecture, utilizing the third dimension (height) to increase storage capacity. Multiple memory chips are stacked vertically with TSVs enabling through-chip connections, effectively transforming a 2D layout into a 3D structure to achieve higher density without increasing footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple memory chips are stacked within a compact package, with each chip containing memory arrays and TSVs embedded within the chip substrate. The TSVs themselves are nested within the chip layers, creating a hierarchical nested arrangement that maximizes space utilization.
2Quantity of substance
If more memory chips are stacked to increase storage capacity, then the data storage capacity increases, but the signal path control complexity increases
Solution Approach 1:
The patent divides the memory system into independently addressable banks within each chip, where each bank can be accessed separately through dedicated TSV signal paths. This segmentation allows parallel access to multiple banks across different chips, managing complexity by creating modular, independently controllable units rather than a monolithic memory structure.
Solution Approach 2:
The patent introduces an intermediary control structure that manages signal routing between the external interface and the stacked memory chips. The TSVs act as intermediaries providing direct vertical signal paths through the chip stack, eliminating the need for complex lateral routing and reducing signal path control complexity.
3Productivity
If through silicon via (TSV) techniques are used to establish signal paths, then the bandwidth and communication efficiency improve, but the manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes TSV parameters including diameter, depth, and spacing to achieve the desired bandwidth while managing manufacturing complexity. By carefully selecting and standardizing these geometric parameters, the design balances the need for high-speed signal transmission through TSVs with the practical limitations of manufacturing precision.
Data Source
AI summary
A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.