Via-Integrated MIM Capacitors for High Capacitance in Tight Footprints
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits scale down, the limited available footprint on a die poses challenges in arranging certain structures effectively, making it difficult to fabricate certain structures in an integrated circuit.
Innovation Solution
The techniques involve forming metal-insulator-metal (MIM) capacitors either around or integrated in via structures, such as trough-silicon vias (TSVs) or nano-scale vias, by configuring the capacitors to directly contact existing conductive structures, thereby optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor structures are used in densely packed integrated circuits, then the available footprint on the die is limited, but achieving sufficient capacitance becomes difficult
Solution Approach 1:
The capacitor structure is nested around the via structure, with the first electrode wrapping around the via sidewall and the second electrode positioned at the via opening. This nesting approach allows the capacitor to utilize the vertical space around the via, achieving sufficient capacitance without occupying additional horizontal footprint on the die.
Solution Approach 2:
The invention transitions from a planar capacitor layout to a three-dimensional structure by positioning electrodes vertically around the via. The first electrode extends along the via sidewall in the vertical dimension, and the second electrode is positioned at the via opening, effectively using the Z-axis to increase capacitance density without expanding the die footprint.
2Quantity of substance
If more capacitor structures are added to increase capacitance, then the capacitance/area performance improves, but the device complexity and fabrication difficulty increase
Solution Approach 1:
The via structure serves dual functions: as a conductive interconnect element and as a template for the capacitor structure. The same via that provides electrical connection also defines the geometry and position of the capacitor electrodes, eliminating the need for separate capacitor fabrication processes and reducing overall device complexity.
Solution Approach 2:
The capacitor structure is merged with the via structure by positioning the first electrode around the via sidewall and the second electrode at the via opening. This combination allows both the via's interconnect function and the capacitor's energy storage function to coexist in the same spatial location, simplifying the overall device architecture.
3Area of stationary object
If capacitor structures are integrated around existing via structures, then space efficiency is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The via structure is formed first, establishing a predefined geometric template. Subsequent capacitor electrodes are then deposited around this pre-formed via, using its sidewall and opening as natural alignment references. This preliminary formation of the via eliminates the need for separate alignment steps and reduces manufacturing precision requirements.
Solution Approach 2:
The via structure serves as its own alignment reference for the capacitor electrodes. The first electrode is positioned around the via sidewall and the second electrode at the via opening, using the via's own geometry to define the capacitor's spatial configuration. This self-alignment mechanism eliminates the need for external alignment marks or complex positioning procedures.
Data Source
AI summary
Techniques are provided herein for forming one or more MIM capacitors either around or integrated in via structures. The via structures may be through-semiconductor via (TSV) structures that extend through a relatively thick portion of a semiconductor substrate, or may be nano-scale via structures that extend through a given device layer of a die. In an example, the capacitor is formed along the outside of a TSV and extends along an entire height of the TSV such that the TSV directly contacts a first electrode of the capacitor. In another example, a capacitor is formed in-line with a portion of a nano-scale via such that a first electrode of the capacitor directly contacts the top surface of portion of the via. In another example, a capacitor is formed directly adjacent to a nano-scale via such that a first electrode of the capacitor directly contacts a sidewall of the via.