TSV Notch Liner Structure for Pad-Safe 3D Interconnects
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Solution Overview
Problem
The formation of through-substrate vias (TSVs) in 3D integrated circuits faces challenges in achieving improved electrical performance due to issues in forming vertical interconnections through substrates, including poor cross-sectional profiles and potential damage to conductive pads during etching processes.
Innovation Solution
A method involving a two-step etching process to form a through substrate via, where a dielectric liner material fills the notch in the via opening, followed by deposition of a diffusion barrier and seed layer, ensuring a smoother profile and minimizing damage to conductive pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional single-step etching process is used to form through-substrate vias, then the process is simpler and faster, but the cross-sectional profile is poor and conductive pads are damaged
Solution Approach 1:
The etching process is divided into two distinct steps: a first etching step that forms an initial via opening with a notch, and a second etching step that extends the via opening through the substrate. This segmentation allows each step to be optimized independently, achieving better cross-sectional profiles while controlling damage to conductive pads.
Solution Approach 2:
A dielectric liner is deposited on the inner sidewall of the via opening before the etching process. This preliminary action protects the conductive pad from plasma-induced damage during etching and provides a foundation for subsequent barrier and seed layer deposition, enabling better profile control.
2Reliability
If etching is performed directly without dielectric liner deposition, then the process is simpler, but plasma-induced damage to conductive pads occurs
Solution Approach 1:
A dielectric liner is deposited on the inner sidewall of the via opening before the etching process. This preliminary action protects the conductive pad from plasma-induced damage during etching and provides a foundation for subsequent barrier and seed layer deposition, enabling better profile control.
Solution Approach 2:
The dielectric liner acts as an intermediary layer between the plasma etching environment and the conductive pad, shielding the pad from direct plasma exposure and preventing damage while still allowing the etching process to proceed effectively.
3Manufacturing precision
If the via opening is formed without a notch, then the etching process is simpler, but the cross-sectional profile is poor
Solution Approach 1:
The via opening is formed with a notch feature that divides the via into upper and lower regions with different cross-sectional profiles. The upper region has a wider opening for better access, while the lower region tapers to provide structural support and control overhang, achieving an optimized profile that would be difficult to obtain with a simple cylindrical via.
Solution Approach 2:
The via opening features an asymmetric notch geometry where the upper portion has a different cross-sectional area than the lower portion. This asymmetry allows the via to accommodate different requirements at different heights: wider opening for deposition access at the top, and tapered profile for mechanical stability at the bottom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in a better cross-sectional profile for TSV formation, reducing plasma-induced damage to conductive pads and enhancing electrical performance in 3D integrated circuits.
Implementation Method 1
A dielectric liner material is formed in the via opening to laterally cover the semiconductor substrate
Implementation Method 2
A via opening is formed to penetrate through a semiconductor substrate... The via opening is extended by removing portions of the dielectric liner material
Data Source
AI summary
A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.