TSV Output Timing Control in Stacked Core Dies
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Solution Overview
Problem
3D memory devices face data transfer conflicts due to timing overlap caused by bias temperature instability (BTI) degradation in metal oxide semiconductor field effect transistors (MOSFETs) of TSV data output circuits, leading to gaps in seamless data transmission between core dies.
Innovation Solution
Implementing a control circuit block with an aligner delay circuit and output control circuit that generates synchronized enable and reset signals (RdTxEn and Rclkrst) to manage TSV data output, using analog delay control for RdTxEn and clock synchronous control for Rclkrst to prevent conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple core dies share common TSVs for data transmission, then chip size is reduced and bandwidth is increased, but data transfer conflicts occur due to timing overlap
Solution Approach 1:
The patent applies preliminary action by adjusting the timing of enable and disable signals in advance to prevent timing overlap. Specifically, the disable signal timing is adjusted to occur before the next enable signal, proactively preventing data transfer conflicts before they can occur. This timing adjustment ensures seamless TSV data transfer while maintaining reliable operation with shared TSVs.
2Productivity
If TSV data output circuit operates continuously to maintain high speed data rate, then productivity is improved, but timing overlap occurs due to BTI degradation
Solution Approach 1:
The patent applies feedback by continuously monitoring the timing of enable and disable signals and adjusting the timing accordingly to compensate for BTI degradation. The system detects timing drift caused by continuous operation and dynamically adjusts signal timing to maintain accurate synchronization, ensuring both high data transfer speed and timing accuracy are maintained over time.
3Duration of action of moving object
If enable pulse signal has low clock duty to extend low state duration, then write operation time is improved, but disable timing delays increase due to BTI degradation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the timing parameters of enable and disable signals to compensate for BTI degradation effects. The system modifies signal timing characteristics in response to observed degradation, maintaining accurate timing control despite the extended low state duration required for write operations. This ensures that disable timing delays do not accumulate and cause conflicts.
Data Source
AI summary
Embodiments of the disclosure provide an apparatus comprising: a plurality of TSVs; a plurality of core dies stacked with one another; and an output control circuit. Each core die includes a data output circuit coupled to one or more TSVs to output read data. The data output circuit includes a data splitter to provide first and second complementary read data in parallel based on the read data, an output data latch to latch the first and second read data, and an output data buffer to receive the first and second read data from the output data latch and drive the TSVs based on the first and second read data. The output control circuit provides a first reset signal to the output data buffer and a second reset signal to the data splitter or the output data buffer to disable the output of the read data to the TSVs.