Silicon Interposer TSV Overlay Tolerance via Alignment Marks
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Solution Overview
Problem
The pick and place operation in fan-out wafer level package (FOWLP) manufacturing introduces lateral variations during die or interposer placement, leading to potential defective electrical connections between through-substrate via structures and redistribution layers, resulting in yield losses due to alignment errors.
Innovation Solution
A chip package structure with a silicon interposer featuring through-substrate via structures and package-side metal pads that provide enhanced overlay tolerance, including an epoxy molding compound interposer frame and die-side redistribution structures, to minimize the impact of placement errors and ensure reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pick and place operation is used to position die or interposer, then manufacturing efficiency is improved, but placement precision deteriorates with lateral variations on the order of 5 microns or greater
Solution Approach 1:
The patent introduces an intermediary alignment structure consisting of alignment marks formed on the carrier substrate and corresponding alignment features on the interposer. This intermediary alignment system mediates between the pick-and-place operation and the final via-to-redistribution-layer alignment, compensating for placement variations through additional alignment steps that occur after die attachment but before via formation.
Solution Approach 2:
The patent performs preliminary formation of alignment marks and alignment features before the pick-and-place operation. These pre-formed features establish a reference framework that enables subsequent alignment adjustments, allowing the system to compensate for placement errors that will occur during the mechanical pick-and-place process.
2Quantity of substance
If pitch of through-substrate via structures is reduced to 10 microns, then device density is improved, but sensitivity to placement errors increases causing defective electrical connections
Solution Approach 1:
The alignment marks and alignment features serve as intermediary reference structures that enable precise positioning of the interposer relative to the carrier substrate even when via pitch is reduced to 10 microns. This intermediary alignment system provides a coarse-to-fine positioning mechanism that maintains electrical connection reliability despite the reduced margin for error.
Solution Approach 2:
The patent changes the parameter of via pitch to 10 microns to increase device density, and simultaneously introduces a new parameter system (alignment marks and alignment features) that compensates for the increased sensitivity to placement errors, allowing both high density and high reliability to be achieved.
3Productivity
If placement errors occur during pick and place operations, then manufacturing speed is maintained, but yield decreases due to defective electrical connections
Solution Approach 1:
The alignment mark system acts as a mediator that enables post-placement alignment correction without requiring slower, more precise pick-and-place operations. This allows the manufacturing process to maintain high-speed mechanical placement while achieving high yield through subsequent alignment and reflow steps that correct placement errors.
Solution Approach 2:
The patent performs preliminary attachment of the interposer to the carrier substrate using standard pick-and-place operations, then performs subsequent alignment and reflow operations to correct placement errors. This sequence maintains manufacturing speed by using fast initial attachment while achieving high yield through corrective steps.
4Extent of automation
If mechanical pick and place operation is used, then automation level is improved, but alignment precision deteriorates due to inherent mechanical variations
Solution Approach 1:
The alignment marks and alignment features serve as intermediary reference structures that enable automated optical or mechanical alignment systems to achieve high precision after the automated pick-and-place operation. This two-stage automated approach maintains high automation level while achieving the alignment precision needed for 10-micron via pitch.
Solution Approach 2:
The patent replaces reliance on purely mechanical pick-and-place precision with an optical or measurement-based alignment system that uses alignment marks and features. This substitution allows automated mechanical placement to be followed by more precise optical alignment, maintaining high automation while achieving superior alignment precision.
Data Source
AI summary
An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.