TSV Semiconductor Package With Nested Die Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Circuit (SoIC) components due to the need for smaller, more creative packaging techniques that can accommodate increasing demands for miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency.
Innovation Solution
The proposed solution involves a process flow for fabricating a semiconductor package that includes singulating a first semiconductor substrate with a through silicon via and attaching it to a second semiconductor substrate. An insulating encapsulation is formed to laterally encapsulate the first semiconductor substrate, and a reveal process is performed to isolate the through silicon via. A dielectric layer and conductor structure are formed to electrically connect the through silicon via, and additional encapsulations and redistribution circuit structures are used to create a stacked semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging techniques are used for SoIC components, then manufacturing process is simpler, but packaging size is larger and integration density is lower
Solution Approach 1:
The patent implements nested packaging by placing the first semiconductor die inside a cavity formed in the second semiconductor die. The first die is fully enclosed within the second die structure, creating a nested configuration that significantly reduces overall packaging volume while maintaining electrical connectivity through conductive vias that pass through the second die substrate.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked packaging by utilizing vertical stacking of multiple semiconductor dies. The first die is positioned within the second die in the vertical dimension, and additional dies can be stacked above, enabling high-density integration by exploiting the third dimension rather than expanding in the horizontal plane.
2Manufacturing precision
If miniaturization is pursued to reduce packaging size, then integration density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent performs preliminary actions by pre-forming cavities in the second semiconductor die before mounting the first die. The cavity is created with precise dimensions and positioning in advance, and conductive vias are pre-established through the second die substrate. This preliminary preparation simplifies the subsequent assembly process and ensures precise alignment without requiring extremely tight tolerances during final packaging operations.
Solution Approach 2:
The patent introduces an intermediary approach by using the second semiconductor die as a carrier substrate that houses the first die within its cavity. The second die acts as an intermediary structure that provides mechanical support, electrical connectivity, and precise positioning for the first die, thereby reducing the stringency of manufacturing precision requirements for the overall package assembly.
3Productivity
If stacked semiconductor package structure is implemented, then integration density and performance are enhanced, but device complexity increases
Solution Approach 1:
The patent merges multiple semiconductor dies into a single integrated package structure where the first die is embedded within the second die. The electrical interconnections are merged through conductive vias that integrate the functionality of both dies into a unified stacked structure, achieving high integration density while consolidating multiple components into one compact package unit.
Solution Approach 2:
The second semiconductor die serves multiple functions: it acts as a structural carrier substrate, provides electrical connectivity through conductive vias, houses the first die within its cavity, and can serve as an additional functional die. This multi-functionality reduces the need for separate packaging components and simplifies the overall package structure despite the stacked configuration.
Data Source
AI summary
A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.