TSV Semiconductor Package Stacking for Compact SoIC Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Circuit (SoIC) components due to the need for smaller, more creative packaging techniques that can accommodate increasing demands for miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency.
Innovation Solution
The proposed solution involves a process flow for fabricating a semiconductor package that includes singulating a first semiconductor substrate with a through silicon via and attaching it to a second semiconductor substrate. An insulating encapsulation is formed to laterally encapsulate the substrates, and a reveal process is performed to isolate the through silicon via. A dielectric layer and conductor structure are formed to electrically connect the via, and additional encapsulations and redistribution circuit structures are used to create a stacked semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional packaging techniques are used for SoIC components, then the packaging process is simpler, but the package size is larger and functionality is limited
Solution Approach 1:
The patent implements package-on-package stacking where a first semiconductor package is placed within or adjacent to a second semiconductor package, creating a nested or stacked configuration. This allows multiple functional units to be integrated in a compact vertical arrangement, increasing functionality while minimizing the horizontal footprint of the overall package assembly
Solution Approach 2:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging by vertically stacking multiple semiconductor packages. This dimensional change from 2D to 3D packaging enables higher integration density and increased functionality without proportionally increasing the package footprint area
2Volume of moving object
If miniaturization is pursued to reduce package size, then compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and bonding of semiconductor dies to substrate boards at the wafer level before final package assembly. This preliminary action establishes precise positional relationships early in the manufacturing process, making subsequent miniaturization and stacking operations more manageable with standard precision equipment
Solution Approach 2:
The patent uses substrate boards as intermediary carriers that hold multiple semiconductor dies in precise configurations. These substrate boards serve as mediation platforms that simplify the alignment process between different packages during stacking, reducing the direct precision requirements between final package components
3Productivity
If wafer-level processing is used, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the packaging process into distinct modular stages: wafer-level die attachment to substrate boards, individual package assembly, and final package-on-package stacking. This segmentation allows each stage to be optimized independently, maintaining high productivity from wafer processing while managing overall process complexity through clear process boundaries
Data Source
AI summary
A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.