TSV Semiconductor Package Structure for Warpage-Resistant Chip Stacking
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Solution Overview
Problem
Semiconductor packages face reliability issues due to warpage during subsequent processes, especially with smaller TSVs and wafers, which can lead to damage and reduced performance.
Innovation Solution
The semiconductor package design includes a base wafer with a thicker substrate and smaller diameter through via electrodes, allowing for increased stacking capacity and improved reliability by reducing warpage and maintaining via electrode characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV size and wafer thickness are decreased to increase stacking capacity, then the number of chips that can be stacked increases, but the wafer becomes more prone to warpage damage
Solution Approach 1:
The patent applies different diameter specifications to through via electrodes at different locations and levels. Base wafer through via electrodes have a first diameter, while semiconductor chip through via electrodes have a second diameter that is different (typically smaller). This local differentiation allows optimization of each level's via electrodes for their specific mechanical and electrical requirements, enabling higher stacking while maintaining reliability.
Solution Approach 2:
The patent changes the diameter parameter of through via electrodes between different levels (base wafer vs. semiconductor chips). By adjusting the diameter parameter locally rather than uniformly, the design accommodates the mechanical constraints of thin wafers while maintaining electrical connectivity and reducing warpage susceptibility in the stacked configuration.
2Quantity of substance
If through via electrode diameter is decreased to increase stacking density, then more vias can fit in the same area, but the via electrode becomes more susceptible to damage
Solution Approach 1:
The patent specifies that base wafer through via electrodes have a first diameter while semiconductor chip through via electrodes have a second diameter. This local quality differentiation ensures that each level's via electrodes are optimized for their specific mechanical and electrical requirements, maintaining integrity while enabling higher density stacking.
Data Source
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AI summary
A semiconductor package includes a base wafer including a first substrate and at least one first through via electrode extending through the first substrate, and a first semiconductor chip provided on the base wafer. The first semiconductor chip includes a second substrate; and at least one second through via electrode extending through the second substrate. The at least one second through via electrode is provided on the at least one first through via electrode to be electrically connected to the at least one first through via electrode. A first diameter of the at least one first through via electrode in a first direction is greater than a second diameter of the at least one second through via electrode in the first direction.