TSV Chip Packaging Structure for Wafer Thinning and Warpage Control
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Solution Overview
Problem
Wafer-level packaging structures face issues with warpage and breakage due to stress, and increasing wafer thickness for mechanical strength complicates size reduction and affects electrothermal and communication performance.
Innovation Solution
A method involving the formation of through-silicon vias (TSVs) with trimming grooves and temporary supporting substrates to manage stress, combined with redistribution layers and under bump metallization, facilitates thinning and bonding to enhance mechanical strength and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the thickness of the thinned wafer is increased to ensure higher mechanical strength, then the wafer is less prone to breakage, but it becomes difficult to reduce the size of the packaging structure and the complexity of the subsequent TSV processes increases
Solution Approach 1:
The patent applies preliminary action by forming trimming grooves on the wafer surface before the thinning process. These grooves are created in advance to pre-determine the final wafer thickness and shape, allowing the wafer to be thinned to a precise thickness without requiring complex post-thinning processing. This preliminary structuring simplifies subsequent TSV processes while maintaining the desired mechanical strength through controlled thickness distribution.
Solution Approach 2:
The trimming grooves create local quality variations in the wafer structure, with different thickness zones optimized for specific functions. The grooves allow certain regions to have reduced thickness for flexibility and heat dissipation, while other regions maintain sufficient thickness for mechanical strength. This localized thickness control enables the wafer to achieve both strength requirements and packaging size reduction without increasing overall process complexity.
2Strength
If the thickness of the thinned wafer is increased to ensure higher mechanical strength, then the wafer is less prone to breakage, but the packaging structure size cannot be reduced
Solution Approach 1:
The trimming grooves create a non-uniform thickness distribution across the wafer, with thinner regions at the edges and sufficient thickness in the active areas. This local quality variation allows the packaging structure to be compact in size while maintaining mechanical strength where needed. The grooves effectively reduce the overall volume and footprint of the packaging structure without compromising the strength of critical regions.
3Adaptability or versatility
If wafer thinning is performed to achieve wafer-level packaging, then integration level and flexibility are improved, but serious warpage problems and breakage occur due to stress
Solution Approach 1:
The trimming grooves are formed before the thinning process as a preliminary action to prevent warpage and breakage. These grooves are strategically positioned to compensate for stress distribution during thinning, creating a pre-stressed structure that maintains flatness even after significant thickness reduction. This preliminary structuring enables aggressive thinning for high integration while preserving wafer stability and reliability throughout the manufacturing process.
Solution Approach 2:
The trimming grooves apply preliminary anti-action by creating a counter-stress structure that opposes the warping forces generated during thinning. The grooves are designed to induce initial curvature or stress patterns that counterbalance the tensile stresses developed when the wafer is thinned, thereby preventing the development of harmful warpage and reducing the risk of breakage during and after the thinning process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of wafer fractures, prevents abnormal warpage, and enhances the electrothermal and communication performance while minimizing packaging size.
Implementation Method 1
bonding the first surface of the wafer to a first supporting substrate
Implementation Method 2
removing the bonding layer by using a chemical solvent
Data Source
AI summary
A chip packaging structure and a method for preparing the same are disclosed. The method includes: providing a wafer having a first surface and a second surface, forming a first redistribution layer on the first surface, wherein the wafer includes TSVs having first ends exposed from the wafer; forming welding pads electrically connected to the TSVs through the first redistribution layer; forming a trimming groove in an edge area of the wafer; bonding the first surface of the wafer to a first supporting substrate, and thinning the second surface of the wafer to expose the second ends of the TSVs; forming, on the second surface of the wafer, solder balls electrically connected to the TSVs through a second redistribution layer; bonding the second surface of the wafer to a second supporting substrate, and peeling off the first supporting substrate; and connecting the welding pads to a semiconductor chip.