3D Semiconductor Package Pad Structure for TSV Adhesion
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Solution Overview
Problem
In 3D chip stack packages, there is a challenge with adhesion between the electrode pad and the passivation layer, as well as between the exposed through silicon vias and the passivation layer, which affects signal transmission and power performance.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with electrode bundles and a backside insulating layer featuring a trench between the through electrodes, where an electrode pad with a protruding portion fills the trench, enhancing adhesion between the pad, the insulating layer, and the through electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a passivation layer is formed to expose the bundle of through silicon vias and an electrode pad is formed on the through silicon vias, then signal transmission characteristics are improved, but adhesion between the electrode pad and the passivation layer and between the exposed through silicon vias and the passivation layer deteriorates
Solution Approach 1:
The patent applies local quality by creating a protruding portion on the electrode pad that specifically fills the trench between through silicon vias. This localized structural modification enhances adhesion only at the critical interface between the electrode pad and passivation layer, while maintaining the overall signal transmission functionality. The protruding portion is formed with different geometry than the standard planar electrode pad, creating a mechanical interlock that improves reliability without compromising electrical performance.
Solution Approach 2:
The patent introduces a vertical dimension by forming a trench between the through silicon vias and filling it with a protruding portion of the electrode pad. This transforms the traditionally planar (2D) electrode pad-passivation layer interface into a three-dimensional structure with increased surface area and mechanical interlocking. The protruding portion extends vertically into the trench, creating additional adhesion pathways that were not present in conventional flat configurations.
2Reliability
If a protruding portion is added to the electrode pad to fill the trench, then adhesion between the electrode pad and the passivation layer is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the trench structure between through silicon vias before forming the electrode pad. This allows the electrode pad material to be deposited in a way that naturally fills the pre-prepared trench, creating the protruding portion in a single formation step. By preparing the trench beforehand, the complexity of forming the protruding portion is reduced, as it becomes an integral part of the electrode pad formation process rather than a separate, complex addition.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of electrode bundles arranged in an array in a first substrate and each having a plurality of through electrodes penetrating the first substrate, a backside insulating layer on a backside surface of the first substrate through which end portions of the through electrodes are exposed, and a plurality of electrode pads respectively provided on the electrode bundles. The backside insulating layer has a first trench formed between the through electrodes of a first electrode bundle. A first electrode pad is disposed on the through electrodes of a first electrode bundle and includes a protruding portion that fills the first trench of the backside insulating layer.