TSV Placement in Semiconductor Chip Pad Area
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Solution Overview
Problem
As the number of stacked semiconductor chips increases, the interconnection space for electrical connections in stack packages decreases, leading to increased package height and size due to the occupation of area by through-silicon via (TSV) insertion units, which also requires additional interconnection lines.
Innovation Solution
The TSV insertion unit is arranged within the pad area, allowing for a reduction in package size by eliminating the need for additional area and optimizing the placement of TSVs and control units to improve signal loading and reduce interference, with TSVs formed in the pad unit and controlled by TSV control units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV insertion units are arranged separately from pad units, then electrical connection is achieved, but chip area increases and interconnection space is reduced
Solution Approach 1:
The patent merges the TSV insertion unit with the pad unit by arranging the TSV insertion unit within the pad area. This integration allows the TSV insertion unit to share the space allocated for pad units, eliminating the need for separate dedicated areas for TSV insertion. As a result, the overall chip area is reduced while maintaining the electrical connection function through the integrated structure.
2Productivity
If the number of stacked semiconductor chips is increased, then integration is improved, but interconnection space is reduced and package height increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple semiconductor chips in the third dimension. This allows the system to achieve higher integration without proportionally increasing the planar footprint. The TSV (through-silicon via) technology enables vertical interconnection between stacked chips, transforming the interconnection approach from primarily planar to three-dimensional, thereby improving integration while managing interconnection space efficiency.
3Reliability
If TSV insertion units occupy predetermined area, then TSV function is achieved, but chip size inevitably increases
Solution Approach 1:
The patent makes the pad unit area serve multiple functions by integrating the TSV insertion unit within it. The pad unit area simultaneously accommodates both the pad unit elements and the TSV insertion unit, allowing these different functional elements to share the same spatial region. This multi-functional use of space enables the TSV function to be achieved without requiring additional dedicated area beyond what is already allocated for pad units.
Data Source
AI summary
Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.