Integrated Circuit Package TSV-Pad Co-Formation for Lower Resistivity
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Solution Overview
Problem
Existing semiconductor manufacturing processes require separate steps for forming through-substrate vias (TSVs) and metallization layers, leading to increased manufacturing costs and higher resistivity, which affects electrical conduction and device performance.
Innovation Solution
Concurrently forming TSVs and a first metallization layer using the same processes, eliminating the need for a barrier layer between them, thereby reducing the number of process steps and enhancing electrical conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate steps are used for forming TSVs and metallization layers, then manufacturing process reliability is maintained, but manufacturing cost increases and resistivity increases
Solution Approach 1:
The patent combines the TSV formation process and metallization layer formation process into a single concurrent operation. The barrier layer is formed to line both the TSV walls and the metallization layer simultaneously, eliminating the need for separate barrier layer deposition steps. This merging of processes reduces manufacturing complexity and cost while maintaining electrical performance.
2Device complexity
If separate steps are used for forming TSVs and metallization layers, then process control is simplified, but resistivity increases and electrical conduction deteriorates
Solution Approach 1:
The patent merges the TSV formation and metallization layer formation into a concurrent process where the same barrier layer deposition step serves both functions. This eliminates the interface between separately-formed TSV and metallization layers, removing the high-resistivity barrier that would exist between two distinct metal layers formed at different times.
Solution Approach 2:
The barrier layer acts as an intermediary that simultaneously lines both the TSV and the metallization layer. By forming this single continuous barrier layer during one process step, the patent creates direct electrical contact between the TSV fill metal and the metallization layer metal, improving electrical conduction while the barrier layer still provides necessary protection against diffusion and void formation.
3Reliability
If barrier layer is removed between TSV and metallization layer, then electrical conduction improves, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the barrier layer from being a separate, discrete layer between TSV and metallization layer, and instead incorporates it as a continuous lining formed during the TSV formation process itself. This extraction of the barrier layer from the interfacial position eliminates the need to remove it for electrical contact, as the barrier layer is now part of the TSV structure rather than a separate component.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first wafer, where forming the first wafer includes forming a plurality of first dielectric layers over a semiconductor substrate, depositing a second dielectric layer over the plurality of first dielectric layers, forming a first opening that extends through the second dielectric layer, the plurality of first dielectric layers, and partially through the semiconductor substrate, filling the first opening with a first Bottom Anti-Reflective Coating (BARC) layer, etching portions of the first BARC layer and the second dielectric layer to form a second opening, where the second opening overlaps and exposes a remaining portion of the first BARC layer in a remaining portion of the first opening, removing the first BARC layer, and concurrently forming a first through substrate via (TSV) in the remaining portion of the first opening and a first conductive pad in the second opening.