TSV Pad Sizing for Signal Integrity and Power Stability
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Solution Overview
Problem
In semiconductor devices, the integration of front end and back end units in multi-chip packages faces challenges in increasing memory capacity and speed due to parasitic capacitance issues caused by through silicon vias (TSVs), which affect signal quality and power source stability.
Innovation Solution
The semiconductor device employs through silicon vias with differently sized pads for power and signal systems, where the power source pad is larger to reduce parasitic resistance and increase capacitance, while the signal pad is smaller to minimize parasitic capacitance, allowing for stable power supply and high signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through silicon vias (TSVs) are used to connect stacked memory chips, then memory capacity and operation speed can be increased, but parasitic capacitance is generated between the TSV and semiconductor substrate which degrades signal quality
Solution Approach 1:
The patent applies local quality by differentiating the pad structure based on its function: signal pads are made smaller to reduce parasitic capacitance and maintain signal quality, while power source pads are made larger to increase capacitance and stabilize power supply. This localized differentiation resolves the contradiction by optimizing each pad type for its specific purpose rather than using a uniform design.
Solution Approach 2:
The patent segments the pad structure into distinct signal pads and power source pads with different sizes. By separating the functions of signal transmission and power supply into distinct pad regions, the patent allows independent optimization of each function, thereby resolving the contradiction between high-speed operation and signal quality maintenance.
2Reliability
If the pad size connected to TSV is increased to reduce parasitic resistance, then power source stability improves, but parasitic capacitance increases which degrades signal quality
Solution Approach 1:
The patent resolves this contradiction by applying local quality through functional differentiation of pads: power source pads are enlarged to increase capacitance and improve power stability, while signal pads are kept small to minimize parasitic capacitance and maintain signal quality. This localized optimization allows each pad type to achieve its specific performance goal without compromising the other function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the power source potential and prevents signal quality degradation by optimizing the size of pads connected to TSVs, enabling increased memory capacity and operation speed in semiconductor devices.
Implementation Method 1
A parasitic capacitance is generated between the semiconductor substrate (a ground potential) and the TSV (a signal or a power source)
Implementation Method 2
The parasitic capacitance needs to be as small as possible because it causes a negative influence on the TSV of a signal system such as degrading its signal quality
Data Source
AI summary
A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.