Through Silicon Via Partial Metallization Hydrophobic Passivation

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Solution Overview

Problem

The formation of cracks in through silicon vias due to thermal expansion mismatch between underfill materials and metallization layers in semiconductor devices leads to reduced efficiency and lifetime, as well as potential leakage and humidity ingress.

Innovation Solution

A method involving the formation of a trench in a semiconductor body with an etch stop layer, coating the inner walls with an isolation layer, depositing a partial metallization layer, and applying a passivation layer to create a through silicon via with hydrophobic or superhydrophobic inner surfaces, reducing material usage and stress, and enhancing mechanical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the through silicon via is completely filled with metallization layer, then electrical contact is achieved, but stress is induced due to thermal expansion mismatch causing delamination and cracks

Engineering Contradiction:

Improveelectrical contact reliabilityVSAvoidstructural integrity of through silicon via

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The metallization layer is deposited to partially fill the through silicon via rather than completely filling it. This partial filling approach provides sufficient electrical contact functionality while reducing the volume of metallization material present, thereby minimizing the stress induced by thermal expansion mismatch between the metallization layer and surrounding materials during temperature cycling.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The invention changes the filling parameter of the through silicon via from complete to partial. By controlling the deposition process to achieve only partial filling, the stress generated due to differential thermal expansion is reduced, preventing delamination and crack formation while maintaining electrical connectivity.

Inventive Principle:

Principle #35Parameter changes

2Strength

If underfill material is used to attach semiconductor device to carrier, then mechanical support is provided, but stress is induced during processing due to thermal expansion mismatch

Engineering Contradiction:

Improvemechanical support of semiconductor deviceVSAvoidthermal stress in through silicon via

Core Design Contradiction:

StrengthVSStress or pressure

Solution Approach 1:

By partially filling the through silicon via with metallization layer, the invention reduces the volume of stress-prone material while maintaining structural support functionality. This allows the underfill material to provide mechanical support without inducing excessive stress in the through silicon via structure.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If cracks occur in through silicon via materials, then electrical leakage and humidity ingress occur, but the invention aims to prevent cracks

Engineering Contradiction:

Improveprotection against leakage and humidityVSAvoidcrack resistance of through silicon via

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The invention applies preliminary anti-action by partially filling the through silicon via with metallization layer before subsequent processing steps. This preventive measure reduces the stress concentration that would otherwise lead to crack formation, thereby preventing electrical leakage and humidity ingress before they can occur.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

By changing the filling parameter from complete to partial, the invention fundamentally alters the stress distribution in the through silicon via, preventing crack initiation and propagation that would lead to reliability failures.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces mechanical stress and adhesion between the underfill material and the through silicon via, preventing crack formation and enhancing the semiconductor device's mechanical stability and operational efficiency while allowing a stable connection with the carrier.

Implementation Method 1

inner surfaces that are adjacent to the inner volume are treated to be hydrophobic at least in places

Methodology Applied

Scientific EffectHydrophobic treatment: Hydrophobe

Data Source

PatentUS11139207B2Method for manufacturing a semiconductor device and semiconductor device

Publication Date: 2021.10.05 AUSTRIAMICROSYSTEMS AG

AI summary

A method for manufacturing a semiconductor device comprises the steps of providing a semiconductor body with a main plane of extension, and forming a trench in the semiconductor body from a top side of the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body. The method further comprises the steps of coating inner walls of the trench with an isolation layer, depositing a metallization layer within the trench, and depositing a passivation layer within the trench such that an inner volume of the trench is free of any material, wherein inner surfaces that are adjacent to the inner volume are treated to be hydrophobic at least in places. Furthermore, a semiconductor device is provided.