Through-Substrate Via Passivation for Interconnect Contamination Blocking

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Solution Overview

Problem

Conventional semiconductor packaging technologies face challenges in preventing contamination from entering interconnect layers during through substrate via formation, which can damage metallization patterns and dielectric layers, leading to performance issues.

Innovation Solution

Incorporating a passivation layer, such as a nitride layer or undoped silicate glass, between the through substrate via and the interconnect structure to block contaminants like moisture and chemicals, thereby preventing damage to the metallization patterns and dielectric layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If through substrate via formation is performed without additional protective layers, then manufacturing process is simpler, but interconnect layers are damaged by contaminants

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidinterconnect layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A passivation layer is formed over the interconnect structure before the through substrate via etching process. This preliminary protective action prevents contaminants from entering and damaging the interconnect layers during via formation, eliminating the need for complex post-protection measures while ensuring interconnect integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The passivation layer acts as an intermediary barrier between the etching process and the interconnect layers. It selectively protects the interconnect structure from contaminants while allowing the through substrate via to be formed, thus mediating between the conflicting requirements of via formation and interconnect protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If passivation layer is added to protect interconnect layers, then interconnect integrity is improved, but device complexity increases

Engineering Contradiction:
Improveinterconnect layer integrityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The passivation layer serves multiple functions simultaneously: it protects interconnect layers from contaminants during via formation, provides a planar surface for subsequent processing, and can be patterned to define via locations. This multi-functionality reduces the need for additional separate protective structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If passivation layer is used during via formation, then contamination is blocked, but manufacturing steps increase

Engineering Contradiction:
Improvecontamination preventionVSAvoidmanufacturing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The passivation layer formation is merged with the existing interconnect structure fabrication process. The same deposition equipment and process conditions used for forming dielectric layers in the interconnect structure are utilized to form the passivation layer, thereby minimizing additional manufacturing steps and maintaining high productivity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The passivation layer effectively blocks contaminants, ensuring the integrity of the interconnect layers and enhancing the reliability and performance of the semiconductor device by preventing damage during the formation of through substrate vias.

Implementation Method 1

Incorporating a passivation layer, such as a nitride layer or undoped silicate glass, between the through substrate via and the interconnect structure to block contaminants like moisture and chemicals

Methodology Applied
Scientific EffectPhysical barrier (passivation):

Data Source

PatentUS20240379439A1Semiconductor device and method
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379439A1 patent drawing
  • US20240379439A1 patent drawing
  • US20240379439A1 patent drawing

AI summary

An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.