TSV Pillar Interconnect with Dual Diffusion Barrier
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Solution Overview
Problem
The existing methods for attaching integrated circuit chips to substrates, such as C4 bumps and copper pillars, face challenges with mechanical and thermal stress, particularly at reduced pitch sizes, leading to potential defects and degradation due to coefficient of thermal expansion mismatches and increased fatigue stresses.
Innovation Solution
The method involves etching through-substrate vias (TSVs) in semiconductor substrates, depositing diffusion barrier layers, and filling them with conductive material to create TSV pillars that connect chips, providing a robust and scalable interconnection solution by mitigating thermal stresses and reducing electromigration concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used for chip attachment, then mechanical strength and thermal reliability are improved, but as contact pad pitch is reduced, solder bump sizes must be reduced which weakens mechanical and thermal properties
Solution Approach 1:
The patent changes the material parameter from solder to copper, and the structural parameter from bump to pillar with TSV integration. This allows maintaining larger cross-sectional area even at reduced pitch, thereby preserving mechanical and thermal reliability while enabling finer pitch configurations
Solution Approach 2:
The patent employs a composite structure combining copper pillar, TSV, and multiple barrier/insulation layers. This composite approach allows each layer to address specific requirements: copper provides conductivity and strength, TSV provides structural support and stress distribution, while barrier layers prevent diffusion, collectively solving the reliability-pitch contradiction
2Productivity
If copper pillar bumps are used to reduce pitch, then scalability is improved, but coefficient of thermal expansion mismatch causes high shear stresses and increases probability of C4 interconnection defects
Solution Approach 1:
The patent transitions from surface-mounted copper pillars to vertically-integrated TSV structures that extend through the substrate thickness. This dimensional change allows the interconnection to accommodate thermal stresses through the depth dimension, reducing shear stresses at the bond interface while maintaining scalability
Solution Approach 2:
The TSV acts as an intermediary structure between the copper pillar and the substrate, providing a gradual transition zone that accommodates CTE mismatch. The TSV's vertical extension and integrated structure distribute thermal stresses more evenly, reducing the probability of interconnection defects while maintaining scalability
3Ease of operation
If TSV holes are etched completely through the substrate, then interconnection is achieved, but mechanical strength of the substrate is reduced
Solution Approach 1:
The patent applies partial action by etching TSV holes only to a specific depth that does not completely penetrate the substrate thickness. This partial etching provides sufficient interconnection capability while leaving the substrate intact, thereby maintaining mechanical strength while achieving the required interconnection function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mechanical strength and thermal reliability of chip connections, reducing the likelihood of defects and degradation by using dual diffusion barrier layers to prevent conductive material diffusion and electrical leakage, while allowing for reduced pitch and minimized strain in interconnections.
Implementation Method 1
Deposit a first diffusion barrier layer on the semiconductor substrate at a periphery of the TSV hole. Subsequently deposit a second diffusion barrier layer on a surface of the insulation layer
Data Source
AI summary
The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.