Electroless Ni-Cu TSV Plating via Polysilicon Mediator
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Solution Overview
Problem
Current technologies face challenges in achieving conformal metal coatings with good adhesion in high aspect ratio via holes and efficient self-aligned routing patterns, particularly due to non-conformal deposition, expensive and slow processing methods, and complexity in wet etching, which limits the feasibility of batch processing and results in costly and complex procedures.
Innovation Solution
The method employs electroless plating using open via holes with a polysilicon base, selectively depositing Ni and forming a silicide barrier layer, followed by copper plating, allowing for simultaneous self-alignment and continuous coverage of routing structures without the need for etching seed or barrier layers, enabling batch processing and hermetically sealed via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sputtering techniques are used for metal via deposition, then the deposition process is simple and fast, but the deposition is non-conformal resulting in poor step coverage on walls
Solution Approach 1:
A polysilicon layer is deposited as an intermediary base layer before the metal deposition. This polysilicon layer serves as a mediator that enables conformal electroless metal plating on the high aspect ratio via walls, solving the poor step coverage issue while maintaining production efficiency
Solution Approach 2:
The invention changes the deposition method from physical vapor deposition (sputtering) to electroless chemical deposition. This parameter change in the deposition mechanism enables conformal coating on high aspect ratio structures while maintaining batch processing capability
2Manufacturing precision
If ALD or (MO)CVD technologies are used to improve step coverage, then conformal deposition is achieved, but the process becomes expensive and slow with no batch processing capability
Solution Approach 1:
The polysilicon layer acts as an intermediary that enables subsequent electroless metal plating to achieve conformal deposition. This approach allows batch processing unlike ALD or (MO)CVD, as electroless plating can process multiple wafers simultaneously while maintaining good step coverage
Solution Approach 2:
The invention replaces the mechanical/physical deposition processes (ALD, (MO)CVD) with a chemical electroless plating process. This substitution enables batch processing capability while achieving conformal deposition, avoiding the productivity limitations of the other technologies
3Ease of manufacture
If electrodeposition is used for high aspect ratio blind via holes, then the process is simple, but wetting of holes is difficult and chemistry delivery into holes is problematic
Solution Approach 1:
The polysilicon layer serves as an intermediary that improves wetting of the via walls. Its presence enables better contact between the plating chemistry and the via walls, allowing reliable metal deposition even in high aspect ratio structures
Solution Approach 2:
Instead of trying to force chemistry into closed blind vias (which causes wetting problems), the invention uses open via holes that extend through the entire substrate. This inversion of the via structure allows easy access for chemistry delivery while maintaining process simplicity
4Ease of manufacture
If wet etching of seed layer and barrier layer is performed after Cu electroplating, then routing patterns can be defined, but the process becomes complex and expensive
Solution Approach 1:
The routing patterns are defined in the polysilicon layer before the metal deposition steps. This preliminary definition eliminates the need for subsequent etching of seed or barrier layers, simplifying the overall process and reducing the number of expensive CMP and etching steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective batch processing, improved wetting during plating, and the manufacture of rigid TSV wafers with hermetically sealed via structures, achieving smaller feature sizes and more efficient routing patterns compared to prior art methods.
Implementation Method 1
selectively depositing Ni on the patterned first poly-silicon by an electroless process
Implementation Method 2
depositing Cu on the Ni by a plating process
Implementation Method 3
providing an intermediate barrier layer of silicide Si x Ni y by silicidation of the deposited Ni
Data Source
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AI summary
The invention relates to methods of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface. It comprises providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited Cu on the Ni by a plating process. Line widths and spacings < 10 µm are provided on both sides of the wafer.