Through-Silicon Via With PN Junction Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing through silicon via (TSV) structures face challenges in achieving effective insulation for both direct current (DC) and alternative current (AC) to minimize energy losses and crosstalk, especially in high aspect ratio vias with complex topologies.
Innovation Solution
A semiconductor die with a via structure featuring an inner metallic conductor isolated by first and second dielectric layers, surrounded by a diffused doped layer forming a PN junction with the substrate, and a polysilicon layer for improved shielding and impedance control, allowing for co-axial or tri-axial configurations with adjustable characteristic impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via is coated with a dielectric layer and metallic layers for DC insulation, then DC insulation is improved, but AC insulation deteriorates due to parasitic capacitance coupling with the substrate
Solution Approach 1:
The via structure is segmented into multiple functional layers: inner conductor, first dielectric layer, barrier layer, conductive layer, second dielectric layer, and outer conductor. This segmentation allows each layer to perform its specific function, with the dielectric layers isolating the conductive elements from the substrate to reduce parasitic capacitance and energy loss.
Solution Approach 2:
Dielectric layers are introduced as intermediary materials between the conductive elements and the silicon substrate. These dielectric layers act as mediators that electrically isolate the via structure from the substrate, reducing the parasitic capacitance coupling that causes AC energy loss while maintaining DC insulation.
2Productivity
If multiple vias are implemented in a multilayer structure, then integration density is improved, but crosstalk between adjacent vias increases
Solution Approach 1:
Each via is segmented into isolated conductive elements surrounded by dielectric layers, which physically and electrically separate adjacent vias. This segmentation reduces the electromagnetic coupling between neighboring vias, thereby minimizing crosstalk while allowing high integration density in multilayer structures.
Solution Approach 2:
The via structure employs local quality variations through different material layers (dielectric, conductive, barrier) with specific electrical properties at different radial positions. The dielectric layers provide local electrical isolation around each via, reducing crosstalk between adjacent vias while maintaining the overall high-density interconnection structure.
3Area of stationary object
If a via has high aspect ratio to reduce footprint, then area is improved, but manufacturing precision deteriorates due to complex topology
Solution Approach 1:
The via formation process is segmented into multiple sequential steps: etching the hole, depositing dielectric layers, forming barrier layers, and filling with conductive material. This segmentation allows each step to be optimized independently, achieving precise control over the high aspect ratio via structure that would be difficult to achieve in a single step.
Solution Approach 2:
Dielectric layers and barrier layers are deposited preliminarily before filling the via with conductive material. This preliminary action prepares the via structure with proper insulation and adhesion properties, enabling precise manufacturing of high aspect ratio vias by establishing the necessary structural foundation before the final conductive fill.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced insulation and reduced capacitance to the substrate, minimizing energy losses and crosstalk, while enabling adjustable impedance for efficient signal propagation and electrostatic discharge protection, particularly useful in applications like medical implants and high-frequency signal rejection.
Implementation Method 1
surrounded by a diffused doped layer forming a PN junction with the substrate
Implementation Method 2
an inner metallic conductor isolated from a surrounding conductive area by a first dielectric layer and a second dielectric layer
Implementation Method 3
The barrier layer is for example a ruthenium or a tungsten nitride or a titanium nitride layer
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A semiconductor die according to this invention comprises a via realised in a bulk material (2). The via has an inner metallic conductor (28) isolated by a dielectric layer (17, 20) from a surrounding conductive area (16) formed by a deposited layer. The bulk material (2) is chosen in a set of doped semiconductor materials containing n-type and p-type materials. The surrounding conductive area (16) is in contact with the bulk material (2) and the surrounding conductive area (16) is made from a material chosen in a set of doped semiconductor materials containing n-type and p-type materials, the surrounding conductive area material being from one type among the n-type and the p-type, and the bulk material being from the other type among said n-type and said p-type.