TSV Insulation Stack Polish Stop Layer Warpage Control
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Solution Overview
Problem
Conventional through silicon via (TSV) processing in 3D integrated circuits faces challenges such as wafer warpage during chemical mechanical polishing (CMP) and outgassing issues during copper barrier formation, which affect layer uniformity and increase processing costs.
Innovation Solution
A method involving a substrate with TSVs lined with an insulation stack comprising a first insulation layer, a polish stop layer, and a second insulation layer, where a conductive layer fills the TSV and is planarized to stop on the polish stop layer, improving surface planarity and reducing outgassing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If larger and thinner wafers are used to increase performance and reduce cost, then manufacturing cost and performance are improved, but wafer warpage occurs during processing
Solution Approach 1:
The patent applies preliminary action by forming the multi-layer insulation stack (first insulation layer, polish stop layer, and second insulation layer) on the wafer surface before subsequent processing steps. This pre-established structure provides mechanical support and stress distribution that prevents warpage during later CMP and other processing operations, allowing thinner wafers to be used without sacrificing stability
2Productivity
If conventional TSV processing is used, then TSV contacts are formed, but outgassing occurs during copper barrier formation
Solution Approach 1:
The patent introduces an intermediary solution by using a multi-layer insulation stack with specific material compositions that act as a barrier and absorption layer during copper barrier formation. The polish stop layer and second insulation layer serve as intermediaries that capture and contain outgassing products, preventing them from contaminating the processing chamber and allowing continuous processing without chamber evacuation
3Productivity
If wafer warpage is present, then processing continues, but layer uniformity during CMP cannot be controlled
Solution Approach 1:
The multi-layer insulation stack is formed in advance before CMP processing to provide a uniformly polishable surface. The polish stop layer specifically enables precise control of CMP depth, ensuring uniform layer removal across the entire wafer surface even when the underlying substrate has warpage, thereby maintaining manufacturing precision while allowing processing to continue
Data Source
AI summary
A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.