Through Silicon Via Polygon Layout for Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The mismatch in thermal expansion coefficients between copper and silicon in through silicon vias leads to stress concentration and reliability issues, causing performance degradation and cracking, which necessitates a larger keep-out zone for active circuits, limiting the integration density of semiconductor devices.
Innovation Solution
Employing specific layout patterns for through silicon vias, such as hexagonal, octagonal, circular, and honeycomb shapes, to reduce stress-induced strain and minimize the keep-out zone, thereby increasing the active circuit density by optimizing the placement of through silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through silicon vias are used to connect different wafers in three dimensional integrated circuits, then integration density and performance are improved, but stress concentration occurs due to CTE mismatch between copper and silicon
Solution Approach 1:
The patent applies local quality by creating a keep-out zone around through silicon vias where active circuits are prohibited. This localized restriction addresses the stress concentration problem specifically at via locations without limiting the overall integration density of the chip. The keep-out zone radius is optimized to balance stress relief with maximum circuit placement density.
2Reliability
If a keep-out zone is established around through silicon vias to prevent cracking and performance degradation, then reliability is improved, but the area available for active circuits is reduced
Solution Approach 1:
The patent optimizes the keep-out zone radius as a critical parameter to balance reliability and area utilization. By carefully selecting the radius value, the patent minimizes the area lost to keep-out zones while ensuring sufficient distance from stress concentration regions. This parameter optimization allows maximum placement of active circuits within the remaining available area.
3Productivity
If the keep-out zone size is reduced to increase active circuit density, then integration density is improved, but stress-induced strain on adjacent circuits increases
Solution Approach 1:
The patent applies partial action by implementing a moderate keep-out zone that provides sufficient stress protection without being excessively large. This partial restriction allows active circuits to be placed closer to vias than a conservative design would permit, thereby increasing integration density while maintaining acceptable stress levels through the optimized zone size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed layout patterns effectively reduce the keep-out zone area by 15-17% both inside and outside the through silicon via array, enhancing the active circuit layout density and improving the reliability of semiconductor devices.
Implementation Method 1
One advantageous feature of three dimensional integrated circuits is that parasitic losses are reduced by employing through silicon vias
Implementation Method 2
Due to the mismatch between the coefficient of thermal expansion (CTE) of copper and the CTE of silicon, there may be a concentration of stress in the areas adjacent to a through silicon via opening
Data Source
AI summary
A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.