TSV Power Distribution for 3D Stacked Semiconductor Chips
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Solution Overview
Problem
In three-dimensional semiconductor packaging, existing configurations face challenges in efficiently supplying power to high-performance chips with arithmetic circuits, as uniform TSV arrangements increase chip surface area, power consumption, and voltage drop, while peripheral TSV arrangements lead to voltage drops and potential malfunctions.
Innovation Solution
Arranging through-silicon vias (TSVs) around the outer periphery of circuit blocks on the first semiconductor chip to efficiently supply power to stacked chips, with alternating power and ground potential TSVs to reduce voltage drop and enhance power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias are arranged uniformly across the chip surface to supply power, then power distribution is improved, but chip surface area increases and voltage drop occurs
Solution Approach 1:
The chip surface is divided into multiple circuit blocks, and through-silicon vias are segmented and arranged around each circuit block rather than uniformly across the entire chip. This segmentation allows power supply to be localized to where it is needed, reducing overall chip surface area while maintaining reliable power distribution to each circuit block.
Solution Approach 2:
Through-silicon vias are strategically positioned around specific circuit blocks where power is actually consumed, rather than uniformly distributed. This local quality approach ensures power supply reliability at the point of consumption while minimizing unnecessary via locations and reducing total chip surface area.
2Area of stationary object
If through-silicon vias are arranged at the periphery to reduce chip surface area, then chip surface area is reduced, but voltage drop increases causing malfunctions
Solution Approach 1:
Instead of arranging through-silicon vias only at the peripheral edge (one-dimensional approach), the invention positions them in a two-dimensional arrangement around each circuit block. This dimensional change allows vias to be closer to power consumption points without increasing overall chip surface area, thereby reducing voltage drop while maintaining compact design.
Solution Approach 2:
Through-silicon vias are pre-positioned around circuit blocks before final chip assembly, ensuring optimal power distribution paths are established in advance. This preliminary action prevents voltage drop issues by ensuring via locations are optimally determined based on circuit block positions rather than peripheral constraints.
3Reliability
If additional wiring and repeater cells are added to compensate for voltage drop, then power supply reliability is improved, but device complexity increases
Solution Approach 1:
The invention extracts and eliminates the need for additional repeater cells and complex wiring by directly positioning through-silicon vias around circuit blocks. This extraction approach removes unnecessary components that would otherwise be needed to compensate for voltage drop, thereby reducing device complexity while maintaining power supply reliability.
Solution Approach 2:
Through-silicon vias serve as direct intermediaries between power sources and circuit blocks, eliminating the need for intermediate repeater cells and complex wiring networks. This intermediary approach simplifies the power distribution system by creating direct power paths without requiring additional mediating components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes voltage drop and performance reduction, allowing for effective power supply to high-performance chips, optimizing chip surface usage and reducing the need for additional wiring and repeater cells.
Implementation Method 1
a plurality of through-silicon vias that are arranged so as to surround the outer periphery of each of the plurality of circuit blocks and that penetrate the semiconductor substrate, and a second semiconductor chip that is stacked on the first semiconductor chip, and that is supplied with a power source through the plurality of through-silicon vias
Data Source
AI summary
A semiconductor device includes a first semiconductor chip including plural circuit blocks provided on a semiconductor substrate, and plural through-silicon vias that are arranged so as to surround the outer periphery of each of the plural circuit blocks and that penetrate the semiconductor substrate, and a second semiconductor chip that is stacked on the first semiconductor chip, and that is supplied with a power source through the plural through-silicon vias.