TSV Die Power-Domain Layout for Stable 3D Interconnects

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Solution Overview

Problem

Current semiconductor devices face challenges in reducing the occupied area and implementing high-speed communication between semiconductor elements, particularly in systems where multiple elements are vertically stacked using through silicon vias (TSVs), which affects electrical characteristics and power stability.

Innovation Solution

The semiconductor device incorporates a first die with through silicon vias, connecting pads, and a rear wiring layer, including multiple rear wires and connecting wires, to facilitate electrical connections between different physical layer regions and power domains, optimizing the layout to improve electrical characteristics and power stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multiple semiconductor elements are vertically stacked using through silicon vias (TSVs), then the occupied area is reduced and high-speed communication is implemented, but electrical characteristics and power stability deteriorate

Engineering Contradiction:
Improveoccupied areaVSAvoidelectrical characteristics
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The first die is divided into multiple power domains (first power domain and second power domain) with separate power supply paths. Each power domain has dedicated connecting pads and through silicon vias, segmenting the power distribution network to improve electrical characteristics and power stability while maintaining the 3D stacked architecture.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If multiple semiconductor elements are vertically stacked using through silicon vias (TSVs), then the occupied area is reduced and high-speed communication is implemented, but power stability deteriorates

Engineering Contradiction:
Improveoccupied areaVSAvoidpower stability
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The power distribution is segmented into multiple independent power domains within the first die. Each power domain has its own connecting pads and through silicon vias, allowing independent power supply and stabilization, thereby improving overall power stability while maintaining compact 3D stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Rear wiring layers are introduced as intermediary structures between the through silicon vias and the power domains. These rear wiring layers include dedicated power wires that distribute power within each domain, acting as mediators to stabilize power delivery while enabling the compact vertical architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If multiple semiconductor elements are vertically stacked using through silicon vias (TSVs), then high-speed communication is implemented, but electrical characteristics deteriorate

Engineering Contradiction:
Improvecommunication speedVSAvoidelectrical characteristics
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The die is segmented into multiple power domains with dedicated connecting pads and through silicon vias for each domain. This segmentation isolates electrical characteristics within each domain, improving signal integrity and electrical performance while enabling high-speed communication through the TSV-based vertical interconnects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each power domain is configured with local connecting pads and dedicated through silicon vias positioned adjacent to the physical layer regions they serve. This local quality approach optimizes electrical characteristics for high-speed communication by minimizing signal path length and reducing interference between domains.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240290738A1Semiconductor device
Publication Date: 2024.08.29 SAMSUNG ELECTRONICS CO LTD
  • US20240290738A1 patent drawing
  • US20240290738A1 patent drawing
  • US20240290738A1 patent drawing

AI summary

A semiconductor device includes a first die having a first and second physical layer regions adjacent each other, connecting pads and a connecting wire on a lower surface of the first die, a rear wiring layer having a first rear wire on the first die, and through silicon vias penetrating the first die, the through silicon vias including a first and second through silicon vias. The connecting pads include a first and a second connecting pads electrically connected with the first and second physical layer regions respectively, and a first and a second pads electrically connected with the first and second through silicon vias respectively. The first rear wire is electrically connected with the first and second through silicon vias. The connecting wire is electrically connected with the first connecting pad and the first pad.