3D Semiconductor Power Supply Network Design via TSV Optimization
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Solution Overview
Problem
In the manufacturing of semiconductor devices with through-silicon-vias (TSVs), existing technologies face challenges in designing and fabricating power supply networks that ensure all nodes have voltages higher than a reference voltage, leading to potential instability and increased IR-drops due to uneven voltage distribution.
Innovation Solution
A method is developed to determine board wiring characteristics, create an initial network structure with power bumps and through-silicon vias, and iteratively add or rearrange these components to ensure all nodes exceed the reference voltage, minimizing the number of vias and bumps while optimizing voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias and power bumps are added to ensure all nodes have voltages higher than reference voltage, then voltage stability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent performs preliminary voltage analysis and simulation during the design phase to identify nodes that will have voltage drops below the reference voltage. This allows proactive placement of through-silicon vias and power bumps before fabrication, ensuring voltage stability without adding unnecessary components.
Solution Approach 2:
Instead of uniformly distributing through-silicon vias and power bumps across the entire device, the patent applies them locally only at specific nodes where voltage analysis indicates drops below the reference voltage threshold. This targeted approach maintains voltage stability while minimizing device complexity.
2Reliability
If more through-silicon vias and power bumps are used to reduce IR-drop, then power delivery performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent determines the optimal locations for through-silicon vias and power bumps through preliminary voltage analysis and simulation. By identifying critical nodes beforehand, the manufacturing process can focus precision on specific locations rather than requiring uniform high precision across the entire device, reducing overall manufacturing precision requirements.
Solution Approach 2:
The patent optimizes parameters such as via diameter, bump size, and spacing based on the identified voltage drop locations. By adjusting these parameters locally at critical nodes, the patent achieves effective IR-drop reduction without requiring excessive manufacturing precision throughout the entire device.
3Reliability
If the power supply network is optimized to minimize voltage deviation, then device reliability is improved, but design time and computational resources increase
Solution Approach 1:
The patent performs voltage analysis and determines via/bump locations in the design phase using simulation and calculation. This preliminary action identifies critical nodes and optimal component placement before fabrication, ensuring voltage uniformity without requiring iterative adjustments during manufacturing or operation.
Solution Approach 2:
The patent uses simulation models and virtual prototypes to copy and test different power supply network configurations. By evaluating multiple design options in the virtual domain, the patent identifies the optimal configuration that minimizes voltage deviation, reducing the need for physical prototypes and iterative redesigns.
Data Source
AI summary
To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.