Through-Substrate Via Profile for Void-Free Electroplating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing through-substrate vias (TSVs) for integrated chips is that smaller opening sizes, while improving reliability by reducing over-etching and damage to conductive structures, hinder the electroplating process, leading to voids in the TSVs and increased resistance, affecting the chip's electrical performance.
Innovation Solution
A method involving a first etching process to form a wide opening, followed by the formation of a dielectric layer and blocking layers to confine the etchant, allowing a second etching process to create a narrower opening that effectively reduces voids and over-etching, while maintaining a wider TSV for better electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the opening size is reduced to improve reliability by reducing over-etching and damage to conductive structures, then reliability is improved, but the electroplating process is hindered leading to voids and increased resistance
Solution Approach 1:
The patent divides the via formation process into two distinct etching stages: a first etching process that creates an initial opening, and a second etching process that refines the opening to the final dimensions. This segmentation allows the first process to create a larger opening favorable for electroplating, while the second process precisely controls the final opening size to prevent over-etching and damage to conductive structures.
Solution Approach 2:
The first etching process performs a preliminary action by creating an initial opening that is larger than the final required size. This preliminary opening provides sufficient space for effective electroplating, and subsequent blocking layer formation and second etching process then refine the dimensions to the precise final specifications, ensuring both good electroplating conditions and protection against over-etching.
2Object-affected harmful factors
If a smaller opening size is used, then over-etching and damage to conductive structures are reduced, but voids form during electroplating and resistance increases
Solution Approach 1:
The via formation is segmented into two etching processes with different purposes: the first process creates a larger opening optimized for electroplating access, while the second process precisely defines the final opening dimensions. This segmentation ensures the opening is large enough to allow effective electroplating without void formation, while still maintaining controlled dimensions to prevent over-etching and damage to surrounding conductive structures.
Solution Approach 2:
The patent changes the opening size parameter through a two-stage etching process. The first etching process creates an opening with larger dimensions favorable for electroplating, and the second etching process adjusts the dimensions to precise final values. This parameter change approach ensures optimal balance between opening size for electroplating effectiveness and opening size control to prevent over-etching damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and electrical properties of TSVs by minimizing voids and over-etching, ensuring effective electroplating and improved conductivity through the semiconductor substrate.
Implementation Method 1
perform a first etching process to form a first opening through a semiconductor substrate... performing a second etching process to form a second opening extending through the dielectric layer
Implementation Method 2
forming a conductive material within the opening to define a through-substrate via (TSV)
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip (IC). The IC includes a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate. An insulating structure is disposed along inner sidewalls of the semiconductor substrate. The inner sidewalls of the semiconductor substrate extend through the semiconductor substrate. A blocking layer is disposed along inner sidewalls of the insulating structure. A through-substrate via (TSV) includes a first portion and a second portion. The first portion extends from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure. The second portion extends from the first portion to the conductive structure and has a maximum width less than that of the first portion.