TSV Protection Layer Pattern for CMP Deformation Control
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Solution Overview
Problem
Semiconductor devices with through silicon via (TSV) technology face reliability issues due to deformation of TSVs during chemical mechanical polishing (CMP) processes, particularly in the scribe lane region, leading to poor physical characteristics and increased production costs.
Innovation Solution
A semiconductor device with a protection layer pattern structure that includes a scribe lane recess and protruding portions covering adjacent scribe regions, preventing deformation of TSVs during CMP by spacing the protection layer apart from the outermost via structure and reducing deposition thickness, thereby enhancing physical characteristics and reducing production time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMP process is performed to expose TSV, then electrical connection between chips is achieved, but TSV adjacent to scribe lane region bends or falls down
Solution Approach 1:
A protection layer pattern structure is formed on the substrate surface before the CMP process to cover and protect the TSV adjacent to the scribe lane region. This preliminary protective measure prevents the TSV from bending or falling during substrate thinning, while still allowing the CMP process to expose TSV in the die region for electrical connection.
Solution Approach 2:
The protection layer pattern structure is selectively formed only in the scribe lane region adjacent to the TSV, rather than covering the entire substrate. This localized protection approach prevents TSV deformation where needed while maintaining manufacturing efficiency and avoiding unnecessary complexity in other regions.
2Reliability
If protection layer is deposited to cover TSV, then TSV deformation is prevented, but deposition thickness increases production time and cost
Solution Approach 1:
The protection layer pattern structure is formed only in the specific scribe lane region where TSV protection is needed, rather than depositing a complete protective layer across the entire substrate. This localized deposition significantly reduces the deposition thickness required, thereby decreasing production time and cost while still providing adequate TSV protection.
Solution Approach 2:
The protection layer is segmented into a patterned structure with specific geometric features (protruding portions and recesses) rather than a continuous layer. This segmentation allows the protection function to be achieved with reduced material deposition, optimizing both protective capability and manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents TSV deformation during CMP, improving the physical characteristics of semiconductor devices and reducing production costs by minimizing the CMP process time and deposition thickness of the protection layer.
Implementation Method 1
a back side of a silicon substrate in which the TSV is formed may be partially removed and a chemical mechanical polishing (CMP) process may be performed to expose the TSV
Data Source
AI summary
A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.