Semiconductor Package Structure Using TSV and RDL for Signal Integrity
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Solution Overview
Problem
Conventional chip packaging methods, such as ball grid array and pin grid array, increase signal path distance, leading to signal delay and attenuation, and struggle to accommodate high pin counts on smaller chip sizes, while wafer level chip scale packages face challenges in reducing package size and manufacturing costs.
Innovation Solution
A semiconductor device package structure utilizing redistribution layers (RDL) and through silicon via (TSV) techniques, which includes conductive vias, redistribution layers, protective layers, and conductive balls to minimize package thickness and enable high pin count on smaller chips, allowing for efficient signal transmission and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ball grid array or pin grid array packaging is used, then the chip can be mounted on substrate, but the signal path distance increases causing signal delay and attenuation
Solution Approach 1:
The patent transitions from planar signal routing to three-dimensional vertical routing by implementing through-silicon vias (TSVs) that penetrate the substrate thickness direction. This dimensional change allows signals to travel vertically through the substrate rather than laterally across the surface, significantly reducing the signal path distance and improving transmission quality.
Solution Approach 2:
The patent employs a nested structure where redistribution layers are embedded within the substrate thickness, with conductive vias passing through multiple layers. The RDLs are positioned at different depths within the substrate, creating a layered nested configuration that optimizes signal routing while minimizing path length.
2Ease of manufacture
If wafer level chip scale package is used, then production cost decreases and parasitic effects are reduced, but package size and thickness reduction is limited
Solution Approach 1:
The patent utilizes the thickness dimension of the substrate to accommodate multiple redistribution layers and conductive vias, rather than expanding the package footprint in the planar dimensions. This vertical utilization of space enables cost-effective wafer-level packaging while achieving smaller overall package size through optimized three-dimensional structure.
Solution Approach 2:
The patent changes the geometric parameters of the package structure by reducing thickness through efficient vertical stacking of RDLs and TSVs. By optimizing the distribution of conductive layers through the substrate thickness and minimizing the footprint, the package achieves reduced volume while maintaining manufacturing efficiency.
3Adaptability or versatility
If more bonding points are added to accommodate high pin count, then connectivity increases, but signal path distance and complexity increase
Solution Approach 1:
The patent resolves the contradiction between high pin count and signal path length by routing multiple signals vertically through the substrate thickness using TSVs. This three-dimensional routing approach allows numerous bonding points to be accommodated without increasing lateral signal path distance, as all signals traverse the short vertical path through the substrate rather than long lateral paths across the surface.
Data Source
AI summary
The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.