TSV Compression-Redistribution Die for Flexible 3D DRAM Placement
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Solution Overview
Problem
Wafer-to-wafer stacking in high-bandwidth DRAM creates obstructions on the base die, limiting processing unit placement and thermal performance due to TSV/multiplexer/driver circuits, and face-to-face stacking restricts the placement of physical IO interfaces and thermal efficiency.
Innovation Solution
Implement a compression-redistribution die with TSVs at a relaxed pitch between memory dies and the base die, using converter/redistributor blocks to expand TSV pitch and facilitate die-to-wafer stacking, allowing for improved thermal conductivity and KGD testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If wafer-to-wafer stacking is used to support low-pitch TSV connections, then high-bandwidth memory performance is improved, but obstructions are created on the base die that limit processing unit placement
Solution Approach 1:
The invention divides the base die into multiple segments or regions, allowing different areas to serve different functions. Some regions are designated for memory access circuits (TSV/MUX/driver) while other regions are kept clear for processing unit placement, thus resolving the conflict between memory bandwidth requirements and processing unit placement flexibility
Solution Approach 2:
The invention introduces an additional dimensional consideration by utilizing the vertical stacking architecture more effectively. By distributing memory access circuits across multiple stacking layers and utilizing three-dimensional space, the base die surface is freed up for processing unit placement while maintaining high-bandwidth memory connections through the vertical TSV pathways
2Quantity of substance
If face-to-face stacking of high-bandwidth DRAM is implemented on the base die, then memory capacity is increased, but thermal performance of the base die is limited
Solution Approach 1:
The invention introduces thermal interface materials, thermal vias, or heat dissipation structures as intermediary elements between the stacked DRAM layers and the base die. These intermediaries facilitate heat transfer away from the memory stacks, preventing thermal accumulation while maintaining the high memory capacity achieved through face-to-face stacking
Solution Approach 2:
The invention applies different thermal management properties to different regions of the base die and stacked structure. Areas with high memory density receive enhanced thermal conduction pathways, while other regions maintain their original characteristics, thus optimizing overall thermal performance without compromising memory capacity
3Ease of operation
If TSV/multiplexer/driver circuits are added to access TSVs and memory banks, then memory access capability is improved, but obstructions are created that limit processing unit placement
Solution Approach 1:
The invention implements a nested arrangement where memory access circuits (multiplexers and drivers) are integrated within or adjacent to the TSV structures themselves. By nesting these access circuits within the vertical TSV pathways rather than placing them as separate planar elements on the base die surface, the available area for processing unit placement is preserved while maintaining full memory access capability
Data Source
AI summary
A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a base die. The 3D stacked memory package also includes memory dies stacked on the base die and including through silicon vias (TSVs) at a first pitch. The 3D stacked memory package also a compression-redistribution die between the memory dies and the base die. The compression-redistribution die includes second TSVs at a second pitch greater than the first pitch.