TSV Redundancy and Test Select Scheme for Defect Repair
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Solution Overview
Problem
Defects in through-silicon vias (TSVs) connections, such as improper connections, high impedance, and contamination, lead to decreased yield and require complex wiring, occupying significant space in semiconductor devices.
Innovation Solution
A TSV array with redundancy TSVs and a test/domino control logic system that uses selection lines and registers to control coupling, allowing for shifting of signal lines to adjacent TSVs, enabling the repair of defective TSVs by rerouting signals through functional ones, reducing the need for complex wiring and space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy TSVs and test/domino control logic system are added to repair defective TSVs, then yield is improved, but device complexity increases
Solution Approach 1:
The patent pre-configures redundancy TSVs and control logic circuits during manufacturing before defects are known. The system proactively establishes repair pathways using selection lines and domino switch circuits that can be activated later to bypass defective TSVs, thereby improving yield without adding complex wiring during operation.
Solution Approach 2:
The patent introduces selection lines and domino switch circuits as intermediary control elements between the TSV array and functional blocks. These intermediaries enable dynamic routing of signals around defective TSVs by controlling the switching state of domino switches, providing a systematic approach to defect tolerance without requiring complex point-to-point rewiring.
2Reliability
If redundancy TSVs are added to replace defective TSVs, then reliability is improved, but area occupied increases
Solution Approach 1:
The patent designs redundancy TSVs that can serve multiple functions: they act as backup pathways for defective TSVs, provide additional routing options for signal distribution, and can be selectively activated based on which TSVs are defective. This multi-functionality allows the redundancy structure to provide defect repair capability while occupying minimal additional area compared to dedicated backup pathways.
Solution Approach 2:
The patent arranges TSVs in a three-dimensional stacked architecture with multiple layers, allowing redundancy TSVs to be positioned in different vertical layers rather than consuming horizontal plane area. The selection lines extend across layers to control domino switches that route signals between TSVs in different dimensions, enabling efficient use of chip area through spatial exploitation of the 3D structure.
Data Source
AI summary
An apparatus including through substrate vias (TSVs) used to interconnect stacked chips is described. The apparatus according to an embodiment includes a plurality of first selection lines each extending in a first direction; a plurality of second selection lines each extending in a second direction to cross the plurality of first selection lines; and a plurality of a TSV units disposed in intersections of the plurality of first selection lines and the plurality of second selection lines, respectively. Each TSV unit of the plurality of TSV units includes a TSV; a switch coupled to the TSV; and a selection circuit. The selection circuit is configured to control a switching state of the switch responsive to each of an associated one of the plurality of first selection lines and an associated one of the plurality of second selection lines being set to an active level.