TSV Semiconductor Package Reflow Stacking
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Solution Overview
Problem
Conventional 3D semiconductor packaging using through silicon via (TSV) technology faces challenges such as transportation difficulties of thinned bottom dies, warpage of package substrates leading to low yield rates, and inefficiencies in thermal compression bonding processes.
Innovation Solution
A method involving a wafer with contact and backside surfaces, where first dies with conductive vias are mounted and thinned, then cut into combo dies, and stacked on a package substrate using a reflow process without thermal compression bonding, with protective layers and insulating materials to secure and protect interconnections, and external solder balls for encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermal compression bonding is used to mount thinned bottom die, then die mounting is achieved, but transportation of thinned bottom die becomes difficult and warpage of package substrate occurs
Solution Approach 1:
The patent applies preliminary action by forming protective layers on the die surfaces before thinning the bottom die. This protective layer is created in advance to prevent damage during subsequent transportation and handling, eliminating the need to handle fragile thinned die separately. The protective layer is formed prior to the thinning process, ensuring the die structure is reinforced before it becomes vulnerable to damage.
2Productivity
If thinned bottom die is mounted directly by thermal compression bonding, then die stacking is achieved, but yield rate decreases due to warpage and mounting failures
Solution Approach 1:
The patent applies parameter changes by modifying the physical state of the bonding interface through the reflow process. Instead of using traditional thermal compression bonding parameters, the invention uses reflow soldering parameters (temperature profile, time) to activate the solder balls, enabling self-alignment and reducing warpage-related failures. This change in process parameters improves both productivity and manufacturing precision.
Solution Approach 2:
The patent replaces the mechanical thermal compression bonding system with a thermal reflow system. Instead of applying mechanical pressure to force alignment and bonding, the invention uses controlled heating to melt the solder balls, which then naturally align and bond the die to the substrate. This substitution eliminates warpage-induced alignment failures while maintaining high productivity.
3Strength
If conventional thermal compression bonding is used for stacking, then die connection is achieved, but manufacturing efficiency is reduced due to process complexity
Solution Approach 1:
The patent merges multiple process steps into a single reflow process. The protective layer formation, die attachment, and interconnection bonding are all achieved in one reflow operation rather than separate thermal compression bonding steps. This consolidation maintains strong die-to-substrate connections while significantly improving manufacturing efficiency by reducing process complexity and cycle time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances manufacturing efficiency, reduces warpage, and improves yield rates by simplifying the stacking process and using protective layers to secure interconnections, making transportation easier and reducing inefficiencies in the semiconductor packaging process.
Implementation Method 1
mounting a plurality of first die to the contact surface of the wafer... placing the wafer and the plurality of first die in a reflow oven
Implementation Method 2
each of the first die having a plurality of conductive vias formed therein, wherein protruding ends of the conductive vias electrically connect to the pads by the bumps
Data Source
AI summary
The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.