3D IC TSV Reservation Areas for ECO Adaptability
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Solution Overview
Problem
In three-dimensional integrated circuit (3-D IC) designs, implementing engineering change orders (ECOs) that require additional or changed through-silicon via (TSV) interconnects can be challenging due to the limited availability of unused TSVs, leading to potential design errors, increased time, and expense, as existing logic functions and wiring may need to be displaced or reconfigured.
Innovation Solution
A method is introduced to efficiently manage TSV interconnects by reserving and reallocating TSV reservation areas within the 3-D IC design file, allowing for the reuse of spare TSVs or TSV reservation areas to create new electrical interconnections, thereby accommodating ECO specifications without extensive redesign activities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional TSV interconnects are added to accommodate ECO specifications, then design adaptability is improved, but device complexity increases due to the need to displace or reconfigure existing logic functions and wiring
Solution Approach 1:
The patent reserves specific TSV locations and associated logic functions/wiring during the initial design phase before ECO specifications are received. This preliminary reservation of resources allows rapid accommodation of design changes without requiring complex reconfiguration of existing logic functions and wiring, thus improving design adaptability while controlling device complexity
Solution Approach 2:
The patent divides the TSV interconnect structure into discrete, pre-defined reservation areas with associated logic functions and wiring. This segmentation allows individual TSV reservations to be independently activated or deactivated based on ECO requirements, enabling flexible design changes without affecting the entire device structure
2Loss of time
If TSV reservation areas are created in advance, then ECO implementation time is reduced, but semiconductor area is consumed by reserved regions that may not be fully utilized
Solution Approach 1:
The patent designs TSV reservation areas with associated logic functions and wiring that can serve multiple potential purposes depending on ECO requirements. The same reserved infrastructure can be configured for different signal, clock, or power distribution functions, maximizing the utility of the reserved semiconductor area and reducing waste
Solution Approach 2:
The patent creates TSV reservation areas with specific local characteristics (signal, clock, or power distribution capabilities) tailored to anticipated ECO needs. Each reservation area is optimized for its specific function, allowing efficient use of semiconductor area while enabling rapid ECO implementation
3Adaptability or versatility
If existing logic functions and wiring are displaced to accommodate new TSV interconnects, then design flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent pre-establishes TSV reservation areas with associated logic functions and wiring in their final positions during initial design. When ECOs are received, these pre-positioned elements are simply activated or deactivated rather than physically displaced, maintaining manufacturing precision while achieving design flexibility
Solution Approach 2:
The patent creates a dynamic design where TSV reservation areas and associated logic functions can be selectively enabled or disabled based on ECO requirements. This dynamic configuration allows design flexibility without requiring physical displacement of manufactured structures, thus avoiding increased manufacturing precision requirements
Data Source
AI summary
A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.