TSV RFIC Dice with Vertically Integrated Phased-Array Antennas

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Solution Overview

Problem

Current radio-frequency integrated circuits (RFICs) face challenges in miniaturization and signal congestion due to the large form factor and impedance variations between phased-array antenna elements, which hinder efficient operation, especially in high-frequency applications like 60 GHz millimeter-wave communications.

Innovation Solution

The integration of through-silicon via (TSV) RFIC dice with phased-array antenna substrates in a vertically stacked configuration, using TSVs to connect the RFIC die to the antenna elements, allows for a smaller form factor, uniform impedance, and separation of RF and lower frequency functions, reducing signal congestion and enabling efficient operation across a wide frequency range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If phased-array antenna elements are integrated with RFICs in a conventional planar configuration, then the system can operate at high frequencies, but the form factor becomes large and signal congestion occurs

Engineering Contradiction:
Improveform factorVSAvoidsignal congestion
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from a conventional planar configuration to a three-dimensional vertically stacked configuration. The RFIC die is positioned beneath the antenna substrate and connected via through-silicon vias (TSVs), utilizing the vertical dimension to reduce the horizontal footprint while maintaining functional integration. This dimensional change directly addresses the form factor issue without introducing additional signal congestion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If phased-array antenna elements are closely integrated with RFICs, then miniaturization is achieved, but impedance variations between antenna elements increase

Engineering Contradiction:
Improveform factorVSAvoidimpedance uniformity
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent extracts the RFIC functionality from the antenna substrate plane and places it on a separate die beneath the substrate. This separation allows the antenna elements to be optimized for impedance uniformity on the substrate surface while the RFIC die handles signal processing. The TSV connections provide controlled impedance pathways, ensuring that miniaturization does not compromise impedance matching across the phased-array elements.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If RF and lower frequency functions are integrated on the same substrate, then device complexity is reduced, but signal congestion increases

Engineering Contradiction:
Improveintegration levelVSAvoidsignal congestion
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the system into distinct functional components: the antenna substrate containing phased-array elements operating at high frequencies (e.g., 60 GHz), and a separate RFIC die handling lower frequency signal processing. These segments are vertically stacked and connected via TSVs, allowing each component to operate in its optimal frequency range without causing signal congestion to the other, while maintaining a compact integrated form factor.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9653805B2Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates
Publication Date: 2017.05.16 INTEL CORP
  • US9653805B2 patent drawing
  • US9653805B2 patent drawing
  • US9653805B2 patent drawing

AI summary

An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.